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By Paul N.Whatmough , Shidhartha Das, David M,Bull ARM, Cambridge, United Kingdom

Class presentation based on ISSCC 2013- 24.5 : A Low-power 1GHz Razor FIR Accelerator with Time-Borrow T racking Pipeline and Approximate Error Correction in 65nm CMOS. By Paul N.Whatmough , Shidhartha Das, David M,Bull ARM, Cambridge, United Kingdom Presented by: 1 Mahnaz Rasti

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By Paul N.Whatmough , Shidhartha Das, David M,Bull ARM, Cambridge, United Kingdom

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  1. Class presentation based on ISSCC 2013- 24.5 :A Low-power 1GHz Razor FIR Accelerator with Time-Borrow Tracking Pipeline and Approximate Error Correction in 65nm CMOS By Paul N.Whatmough, Shidhartha Das, David M,Bull ARM, Cambridge, United Kingdom Presented by: 1Mahnaz Rasti 1Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran Spring 2013

  2. Outline: • Razor Systems • ANT(Algorithmic Noise Tolerance) Circuits • Combining Technologies • Architecture of the Chip

  3. Outline: • Razor Systems • ANT(Algorithmic Noise Tolerance) Circuits • Combining Technologies • Architecture of the Chip

  4. Razor Systems: One of the more effective and widely used methods for power aware computing is: DVS (Dynamic Voltage Scaling) Voltage 

  5. Razor Systems: • Razor propose a new approach to DVS, based on dynamic detection of circuit timing errors • Key Idea: Tune the supply voltage by monitoring the error rate during circuit operations[1] [1] (MICRO-36), December 2003 - Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation- Dan Ernst

  6. Razor Systems(ex. flip-flop[1]) • Double samples pipeline stages value • Once with a fast clock • Again with a time borrowing delay clock • A metastability-tolerant comparator then validates latch value sampled with fast clock • In the case of a timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. [1] Ref: (MICRO-36), December 2003 - Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation- Dan Ernst

  7. Razor Systems: Figure 1. Pipeline augmented with Razor latches and control lines. Ref:(MICRO-36), December 2003 - Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation- Dan Ernst

  8. Outline: • Razor Systems • ANT(Algorithmic Noise Tolerance) Circuits • Combining technologies • Architecture of the Chip

  9. ANT Circuits: Figure 2 Ref: http://icims.csl.uiuc.edu/~vips

  10. ANT Circuits: • Modify algorithm for system level error control • ANT detects such errors in system output and mitigates their effects on system performance. • Errors are detected by low complexity prediction scheme. Figure 3 Ref:http://icims.csl.uiuc.edu/~vips

  11. ANT Circuits: Figure 4 : Error predictor in ANT Circuits-[http://icims.csl.uiuc.edu/~vips]

  12. Outline: • Razor Systems • ANT(Algorithmic Noise Tolerance) Circuits • Combining technologies • Architecture of the Chip

  13. :Combining technologies • ANT • Rely on imbalance ripple adder and hence limited clock frequency, increasing baseline area and power Razor Systems Low power, fault tolerant High clock frequency Low overheads &

  14. Outline: • Razor Systems • ANT(Algorithmic Noise Tolerance) Circuits • Combining technologies • Architecture of the Chip

  15. Architecture of the Chip Approximate Error Correction Time Borrow Tracking Figure5: FIR accelerator with Razor latches, time-borrow tracking (TBT) and approximate error correction (AEC)- ISSCC 2013 – 24.5

  16. Architecture of the Chip Figure6: FIR accelerator with Razor latches, time-borrow tracking (TBT) and approximate error correction (AEC)- ISSCC 2013 – 24.5

  17. Characteristics: • Tow distinct error correction technique • TBT • AEC • A 1Ghz datapath due to elimination of ripple-carry adders • Energy efficiency improvement of up to 37%

  18. Die: Figure7: Die photo- ISSCC 2013 – 24.5

  19. References: • ISSCC 2013 – 24.5 – “A Low-Power 1GHz Razor FIR Accelerator with Time-Borrow Tracking Pipeline and Approximate Error Correction in 65nm CMOS” - Paul N. Whatmough - ARM, Cambridge, United Kingdom. • (MICRO-36), December 2003 – “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation”- Dan Ernst • “Algorithmic Noise Tolerance for Low Power Signal Processing in the Deep SubMicron Area” - ECE Department University of Illinois at Urbana-Champaign

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