ECE 353 Introduction to Microprocessor Systems

1. ECE 353Introduction to Microprocessor Systems Michael J. Schulte Week 11

2. Administrative Matters • Homework #5 due Monday, April 28th • Quiz #3 on Thursday, May 1st in 3534 EH from 7:15 to 8:30. • Covers Module 5 and first half of Module 6 (weeks 9, 10, and 11) • Similar in format to previous quizzes • Look over education objectives • Review on Monday, April 28th from 5:30PM to 7:00PM in 2534 Engineering Hall. • Reading for week 11 (interrupts and exceptions) • Textbook chapter 8 • ADuC 74-75 • ARM7 2.8-2.10

3. Quiz2 Data • High: 91%, Low: 53% • Avg: 64%, Median: 61% • Grade Breakdown for midterm • 73-100 A • 63-72.9 AB • 58-62.9 B • 55-57.9 BC • 50-54.9 C

4. Topics • Interrupt Concepts • ARM7TDMI Interrupt Handling • ADuC7026 Interrupt Implementation • Interrupt Sources • Interrupt Service Routines (ISRs) • Interrupt Driven Systems • Software Interrupts and Exceptions • Interrupt Priority and Latency • Debugging Interrupt Hardware and Software

5. Why Use Interrupts? • Maximize processor utilization and efficiency • Allow use of sleep/idle states when nothing to do to save power • Minimize latency in responding to complex input/output structures • Facilitate event-driven applications and preemptive multitasking • What is hard about interrupts?

6. Interrupt Primer • Terminology • Basic interrupt hardware (simple diagram) • Interrupt request (IRQ) • Interrupt acknowledge (INTA or IACK) • Interrupt masking • Maskable interrupt • Non-maskable interrupt (NMI) • Interrupt sensitivity • Level-sensitive • Edge-sensitive

7. Interrupt Concepts • Supporting multiple interrupt sources • Polled interrupts – single ISR • Vectored interrupts • Fixed ISR locations • Vector table implementations • Generic implementation • Prioritization • Fixed • Rotating • Hierarchical • Software interrupts and exceptions

8. ARM7TDMI Interrupt Handling • Interrupt modes • IRQ • Banks R13, R14, SPSR • FIQ • Banks R8-R12, R13, R14, SPSR • SWI (software interrupt) discussed later • Interrupt control • CPSR I/F flags • Interrupt processing sequence • Interrupt nesting

9. ADuC7026 Hardware Interrupts • Interrupt sources • Internal peripherals • External IRQ pins • Programmed interrupts • Interrupt sources can be individually programmed to generate either FIQ or IRQ mode entry. • No prioritization of individual sources at a given level

10. ADuC7026 Interrupt MMRs • These MMRs are used to control the interrupt handling • IRQSTA, FIQSTA • Ones indicate that the sources have an interrupt enabled and pending • Used in ISR to determine which device(s) needs service • IRQSIG, FIQSIG • Ones indicate that the source has an interrupt pending • IRQEN, FIQEN • Ones indicate that the interrupt request from the source is unmasked (i.e. the interrupt source is enabled) • IRQCLR, FIQCLR • Write ones to clear the corresponding bit in IRQEN, FIQEN (i.e. mask an interrupt source)

11. ADuC7026 Programmed Interrupts • The programmed interrupt feature allows us to programmatically force an entry into FIQ mode or IRQ mode • Write to SWICFG register, do not need to have programmed interrupt enabled in IRQEN/FIQEN • Note that the use of “SWI” has nothing to do with the ARM7 SWI instruction and supervisor mode

12. Interrupt Service Routines • ISR prerequisites • aduc7026.s • ISR implementation • Context save • Clear IRQ from interrupt source • Allow nesting (if desired) • Handle interrupt • Context restore • Return from interrupt/exception • Interrupt Checklist on course web page • Shared procedures and resources

13. Interrupt Driven Systems • Foreground vs. background tasks. • Events determine the actual order of execution.

14. Software Interrupts & Exceptions • SWI instruction • Exceptions • ARM7TDMI exceptions • Prefetch abort • Data abort • Undefined instruction • Reset • Other common exceptions • Divide error • Single-step • Breakpoint

15. Interrupt Prioritization and Latency • Handling multiple simultaneous interrupts and exceptions • ARM7TDMI exception priorities • Interrupt prioritization schemes • Fixed • Rotating • Tiered (hierarchical) • Interrupt Latency • Definition • ADuC7026 latency specifics

16. Interrupt Issues • Using periodic interrupts to perform iterative tasks • What to do when good interrupts go bad… • Software debugging • Hardware debugging • Real-time issues • Inter-process communication (IPC) issues

17. In-Class Assessment Quiz • What sort of safeguards might you need to design into NMI hardware? • For the ARM7TDMI, describe what happens between an IRQ being asserted and the actual execution of the ISR. • What are the differences between vectored interrupts and polled interrupts?

18. In-Class Assessment Quiz • What is a ‘level-sensitive’ interrupt? • What problems could arise when using a semaphore to control access to a resource used by the main program and an ISR? What ARM7TDMI instruction(s) help handle this issue? • What advantages does the FIQ interrupts have over IRQ interrupts in the ARM7?

19. Wrapping Up • Reading for week 12 • Textbook 7.6-7.10 • Supplement #5 (Learn@UW)

20. Interrupt Terminology • Event • Asynchronous event • Pending interrupt • Interrupt service routine (ISR) • Interrupt driven I/O • Critical code section

21. Interrupt Processing Sequence • CPU recognizes the interrupt • Complete execution of current instruction • Save the current processor context • Modify CPSR for IRQ/FIQ mode entry • Execute IRQ/FIQ mode exception handler • Return to execution of interrupted code

22. Generic Implementation

23. Priority Interrupt Controller

24. ARM7 CPSR • Current Process Status Register (CPSR) • Condition code flags (N, Z, C, V) • Interrupt disable bits (I, F) • Thumb mode enable (T) • Never change directly! • Mode select • These bits cannot be changed in User mode

25. ARM7 SPSR • Suspended Process Status Register (SPSR) • SPSR is only present when the CPU is operating in one of the exception modes • Each exception mode has its own SPSR, since exception handlers may cause other exceptions. • SPSR is a copy of the CPSR immediately before the exception mode was entered. • When returning from the exception, the value in SPSR is used to restore the CPSR to the proper state for the process that was interrupted.

26. ARM7 Register Banking

27. Interrupt Example - Hardware

28. AREA Reset, CODE, READONLY ARM ; Exception Vectors mapped to Address 0. ; Absolute addressing mode must be used. Vectors LDR PC, Reset_Addr LDR PC, Undef_Addr LDR PC, SWI_Addr LDR PC, PAbt_Addr LDR PC, DAbt_Addr NOP ; Reserved Vector LDR PC, IRQ_Addr LDR PC, FIQ_Addr Reset_Addr DCD Reset_Handler Undef_Addr DCD Undef_Handler SWI_Addr DCD SWI_Handler PAbt_Addr DCD PAbt_Handler DAbt_Addr DCD DAbt_Handler IRQ_Addr DCD IRQ_Handler FIQ_Addr DCD FIQ_Handler Reset_Handler ;setup PLL and power control LDR R1, =PLL_MMR_BASE aduc7026.s

29. aduc7026.s LDR R0, =Stack_Top ; Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size ... ; Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size ; Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_Size ; Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size ; Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_USR MOV SP, R0 SUB SL, SP, #USR_Stack_Size ; jump to user code B __main

30. SWI Instruction Reference • SWI • SWI{<cond>} <immediate_24> • RTL if(cond) R14_svc <-address of next instruction after SWI instruction SPSR_svc <-CPSR ; save current CPSR CPSR[4:0] <-10011b ; supervisor mode CPSR[5] <-0 ; ARM execution (T bit) CPSR[7] <-1 ; disable interrupts (I bit) PC <-0x00000008 ; jump to exception vector • Flags are not affected

31. ADuC7026Interrupt Latency

32. ADuC7026Exception Priority