8G1. Scalable Circuits for Supply Noise Measurement

1. 8G1. Scalable Circuits for Supply Noise Measurement Valentin Abramzon, Elad Alon, Bita Nezamfar, and Mark Horowitz Stanford University Rambus Inc.

2. Motivation and Challenges • Scaling leads to drastic reduction in required supply grid impedance • Supply noise a concern even for digital circuits • There are CAD tools to model supply noise • But still too little experimental data • Measuring high-bandwidth supply noise is challenging • 20 GS/s, 8-bit ADC’s aren’t cheap 1mΩ(!)

3. Measurement Approaches – Sub-sampling Oscilloscope • Measure repetitive waveforms: • Collect probability distribution of noise with time: • Don’t have to sample fast, but samplers still need to have high bandwidth to avoid filtering

4. Measurement Approaches – Spectrum Analyzer Measurements • Measure correlation of two samples as a function of τ: • Known as autocorrelation function • Fourier transform is power spectral density (PSD) • Sampling rate can be low • Because autocorrelation is an average property • Noise does not have to be periodic • But need 2 independent high-bandwidth samplers

5. Sampler Design • Previous Solution Overview • Proposed Circuits • Test Chip Implementation and Results • Conclusions

6. Previous S/H-based A/D Converter System Separate, quiet, higher supply VddQ (but not always available) • Buffered S/H output drives the ring oscillator (VCO) supply • Count VCO pulses over time window TWIN to measure frequency • Resolution improves with longer TWIN – but limited by leakage • Leakage exponentially increases with scaling E. Alon, et. al., “Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise," IEEE Symposium on VLSI Circuits, June 2004

7. Sample and Hold Design Issues • PMOS is better for high-bandwidth sampling of Vdd • But if VddQ is not quiet… • …its noise feeds through Cgd and Cdb to VS/H • Have coupling issues with NMOS S/H too • Thick-oxide high-VT devices reduce leakage • But make feedthrough worse if want high bandwidth • Unpleasant feedthrough-bandwidth-leakage trade-off

8. Solution 1 – Cancel Feedthrough in Post-processing • With everything powered up from the measured Vdd • And if leakage is kept low • VS/H = Vdd,sample + Kf· ( Vdd – Vdd,sample ) • Kf is the feedthrough coefficient • VCO-based A/D averages S/H output over TWIN • For TWIN >> TSIGNAL, signal attenuated by ( 1 – Kf ) • For TWIN << TSIGNAL, signal is intact

9. Solution 1 – Cancel Noise Feedthrough in Post-processing • Have an equivalent to a low-pass filter the with H( f ) = 1 - Kf + Kf sinc( TWIN f ) exp( j π TWIN f ) • Can calibrate for Kf: • Apply AC waveform with period TWIN • Attenuation is 1 - Kf • Then apply inverse H( f ) filter in post-processing • Still, have high bandwidth - low leakage trade-off • Especially difficult if don’t have high-VT devices…

10. Solution 2 – Shorten Conversion Window… • …so that sampled voltage does not leak out • Average conversions to improve resolution: • Works because initial VCO phase is random • Adds intrinsic dither to the quantizer • Also works for autocorrelation

11. Solution 2 – Shorten Even More… • If TWIN is so short that input signal stays constant, • Explicit S/H unnecessary • VCO averages noise over TWIN • Model as a running-average filter • Has sinc frequency response: • equivalent 3dB bandwidth f-3dB0.44/TWIN • For example, bandwidth is 10GHz for TWIN 44ps • But each conversion is not very sensitive to Vdd • So need many averages • On-chip averaging helps

12. Solution 2 – Circuit Implementation:Averaging-based System without a S/H ASIC • Instantaneous VCO frequency α instantaneous Vdd • Detect VCO edges over TWIN to measure frequency: • Average number of edges α average Vdd at sampling instants • Look at all ring oscillator phases to increase sensitivity Link C Link D Link B

13. Solution 2 – Delay Generation • TWIN needs to have different dependence on Vdd than VCO period • As long as ramp rate is slower than RC delay, • TWIN is roughly independent of Vdd

14. Outline • Previous Solution Overview • Proposed Solutions • Test Chip Implementation and Results • Conclusions

15. Test Chip Implementation • Both sample and hold and averaging-based systems integrated in a 90nm SOI process • Part of a parallel interface test chip • Two identical channels for autocorrelation • A/D converters are triggered with external pulse generator with variable delays

16. Test Results - ADC Calibration Curves • Buffer in S/H-based system fails at lower voltages • LSB~0.3mV • Averaging-based system works over larger range • Noise sigma is ~1mV for ~106 averages

17. Test Results – Externally Induced Noise • Induced 1MHz square-wave noise on the supply with on-board noise generator • Both subsampled and measured autocorrelation • Corrected for feedthrough in a S/H-based system • Measured Kf of ~0.25 (agrees with simulation)

18. Test Results – Self-Induced Noise • Sub-sampled deterministic noise synchronous with the 500MHz refclk • Differences due to • Averaging-based system being close to strong noise sources • S/H-based system being close to large bypass capacitor (~25nF)

19. Conclusions • Two ways of dealing with scaling issues in on-chip samplers: • S/H-based system • Can cancel feedthrough in post-processing • But requires extra calibration • High bandwidth with low leakage is still hard • Averaging-based system • Simple and easily scales • But requires large number of averages • On-chip averaging helps reduce measurement time • Choice depends on technology • With scaling, averaging-based system becomes more and more attractive

20. Acknowledgements • This work was funded by C2S2, the MARCO Focus Center for Circuit & System Solutions • K. Chang, F. Assaderaghi, and B. Tsang of Rambus, Inc.