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MOSFET Scaling

MOSFET Scaling. ECE G201. next. Most Simple Model: Constant Field Scaling. E = V DD /L after scaling becomes E = (V DD / a )/(L/ a ) …where a >1. Impurity Concentration Scaling must also follow length scaling for depletion widths.

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MOSFET Scaling

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  1. MOSFET Scaling ECE G201

  2. next Most Simple Model: Constant Field Scaling E = VDD/L after scaling becomes E = (VDD/a)/(L/a) …where a>1

  3. Impurity Concentration Scalingmust also follow length scaling for depletion widths Recall, that the source and drain are heavily doped and therefore the junctions are one-sided (n+p for NMOS): W = (2eVDD/qNA)1/2 …unscaled FET W/a = (2eVDD / a2qNA)1/2 = [2e(VDD/a)/qaNA]1/2 Therefore, the doping levels must increase by a factor a if the depletion widths are to scale down.

  4. Historical Scaling“Moore’s Law:” number of transistors/chip doubles every 18 mo. 1 generation: ~18 mo. L decreases by 0.65/generation (a = 1/0.65 = 1.5) VDD decreases by 0.85/generation Therefore, constant field scaling (VDD/L) is not strictly followed.

  5. Generalized Scaling Length: a = 1/0.65 = 1.5 Voltage: b = 1/0.85 = 1.2  Electric field:E increases x1.25 Doping: ba = x1.8 (!) note: not strictly followed

  6. EC EV W Junction Leakage CurrentTunneling current due to highly doped Drain-Body junctions B D IJE Recall: tunneling T = Kexp(-2kW)

  7. Gate Leakage Currenttox 0 means large tunneling current A large oxide capacitance is needed to control the channel charge and subthreshold current: Vch = VGS(Cox’+CB’)/Cox’ …where Cox’ = eox/tox since tox is limited by tunneling, research is focused on alternate gate dielectric materials with larger permittivity (“high-K”).

  8. High-K gate insulator reduces tunneling current by allowing a thicker insulator 0.8 nm

  9. High-K Issues • Large number of interface traps, Qit • impacts VT control and repeatability • Process integration • SiO2 is relatively easy (thermal oxidation of Si) • Potential materials: • HfO2, ZrO2, TiO2,BST….?

  10. Subthreshold Current (revisited)VDD scaling  VT scaling

  11. Total Stand-by PowerPoff = VDD(Ig + IJE + Ioff)

  12. Scaling Directions (I)SOI (DST, depleted substrate transistor) Very thin body region (Tsi = L/3) makes the source and drain spreading resistance (RS) large. Raised S/D improves ID (next) Improves subthreshold slope, S and decreases Ioff Also decreases CjE …and IJE

  13. Raised S/D(i.e., decreased RD, RS)

  14. Switching Speed: High current (ION) but low voltage and low IOFF

  15. Scaling Directions (II)The “FinFET” moves from a single gate to double and triple gate structures.

  16. Advantages: Control of the channel:must be fully depleted!Improved RS, RD due to thicker Si body

  17. Gate prevents “top” gate Fin (30nm) BOX

  18. MOSFET Future (One Part of) • International Technology Roadmap for Semiconductors, 2006 update. • Look at size, manufacturing technique.

  19. Questions? Scaling (a, e) Tunneling Subtheshold Current High-K gate dielectric Spreading Resistance (Raised S/D) FinFETs

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