PIDS Update December 3, 2010 Makuhari , Japan

1. PIDS UpdateDecember 3, 2010Makuhari, Japan PIDS Members Speaker: Kwok Ng (U.S. Chair)

2. PIDS Roster C=Chair, CC=Co-Chair, VC=Vice-Chair

3. Outline • PIDS Mission and Technical Sub-Groups • Logic • Memory: DRAM • Memory: Nonvolatile • Reliability • 2010 Edition Update Summary • Plans for 2011 Edition

4. PIDS = Process Integration, Devices, & Structures • Mission: • Provide physical and electrical requirements and solutions for sustaining IC scaling in digital logic technologies and memory technologies. • Scopes: • Performance (speed, density, power, functionality…) • Structures • Process-integration challenges • Reliability

5. PIDS Technical Sub-Groups • Logic (Leads = Kwok Ng, Ichiro Matsuo) • HP = High Performance (e.g., mP…) • LOP = Low Operating (Dynamic) Power (e.g., notebook…) • LSTP = Low Standby (Static) Power (e.g., cellular…) • Memory: DRAM (Lead = Hirofumi Inoue) • Memory: Nonvolatile (Leads = Rich Liu, Hirofumi Inoue) • Reliability (Lead = Charles Cheung)

6. 2010 Update: Logic Low Operating Power (LOP) Technology Requirements • Power supply voltages Vdd lowered to reduce the dynamic power. • From this change, the speed I/CV values are reduced by amounts ranging 14–34% from those of 2009. These speeds are considered adequate. Low Standby Power (LSTP) Technology Requirements: • Off-current Ioff reduced from 50 pA/mm to 10 pA/mm to decrease the static power. • Power supply voltages Vdd lowered to similar values as those of HP technology to reduce the dynamic power. • From these changes, the speed I/CV values are reduced by the amounts ranging 20–57% from those of 2009. These speeds are considered to be adequate for their functions.

7. 2010 Update: DRAM • Survey had been performed by Japan PIDS. Together with market observations, following changes are made (only in PIDS chapter but not yet in ORTC and other chapters until 2011): • Half-pitch scaling is accelerated by 1 year for the next 5 years. • Structure transition from RCAT to FinFET is delayed by 2 years to 2012. • VCT (vertical channel transistor) will be launched in 2013 and continues till end of roadmap. • Cell size factor transition to 4F2 will be delayed by 2 years. • Support PMOS gate electrode transition to TiN metal gate is delayed by 2 years.

8. 2010 Update: Nonvolatile Memory NAND flash survey had been performed by Japan PIDS. Together with market observations, following changes had been made (only in PIDS chapter but not yet in ORTC and other chapters until 2011): • Half-pitch scaling is accelerated by 1 year. • Product density (in Gb) is accelerated by 1 year. • Introduction of 3-D stacking is delayed by 1 year to 2015. • Transition to 4 bit/cell is delayed by 7 years to 2019. • 2010 Update: Reliability • No update.

9. Plans for 2011 Edition • Since the increase per year in circuit clock frequency has slowed down, on-going discussion with Design TWG and industry on device speed (I/CV) scaling requirements. (i.e., can current I/CV increase of 13%/yr be reduced?) • Add dynamic power metric CV 2 on logic devices (HP, LOP, and LSTP). • Revisit whether we should eliminate LOP device. • Add/use commercial state-of-the-art numerical device simulator for calculating electrical characteristics to supplement MASTAR (analytical).Working closely with Modeling TWG. • Planning to add III-V (for n-channel) and Ge (for p-channel) as alternate channel materials for low-Vdd (low dynamic power) options, i.e., HP & LOP.Product introduction year = 2018.

10. Plans for 2011 Edition (cont’d) • New DRAM survey being performed by Japan PIDS, to be completed Jan/2011. • NAND flash: 1-year pull in. Distinguish 3-D NAND from planar NAND with separate values in half-pitch, MLC, density... • STT MRAM: Consider moving from Potential Solution to Technology Requirements table (as a main-stream technology option).Planning survey, to be completed by March/2011. • (End)