Advanced Digital Circuits ECET 146 Week 6

1. Advanced Digital CircuitsECET 146Week 6 Professor Iskandar Hack ET 221B, 481-5733 hack@ipfw.edu

2. Introduction to Finite State Machines • We will only discuss synchronous Finite State Machines (FSM’s) • Synchronous FSM’s will change state only on a rising or falling clock edge • The simplest Finite State Machine (FSM ) is a counter • Every FSM has an input at a minimum a clock and reset • A simple counter the counts from 0 to 5 and repeats has 6 unique states, which I’ll call s0, s1, s2, s3, s4 and s5 • A simple counter will change state every clock cycle

3. A Simple Bubble Graph for Counter

4. Block Diagram for FSM Clock State Transition Table Outputs Next State Reset Other Inputs Current State

5. Defining State Machines in VHDL • Define Subdesign with Inputs and Outputs as before • Add the state machine type definition • Add the signal definition of state type • Start a process and use a CASE – When to specify state transition • End Process and use a With – Select to define the output for each state

6. VHDL Simple Counter Design Entity with I/O specified Tell Altera to set Up State Machine Define how to go from Current State to Next State Define what the outputs are for Each state

7. Save, Set Project and Compile • Repeat steps as done earlier projects • Save as projname.vhd • Set Project to Current File • Save and Compile

8. Simulate • Open Waveform Editor and add nodes from vwf as before • The only inputs are reset and clk in this project • Also add the variable state to the simulation • Take the reset high for ½ clock cycle and use the clock function to define the clock

9. Node Finder Note – all names not just pins Add the following

10. Simulation Waveform

11. Lab 6 • Design a counter in VHDL that will count the sequence 0,1,3,4,5,6,7,2,0,1,3,… • Simulate the Design and turn in the a copy of the VHD file and Simulation • Create a NEW project with a new name (I used simple_counter)