Circuit Issues for Hitachi-die EEPROMs

1. Circuit Issues for Hitachi-die EEPROMs October 12, 2005 Rod Barto NASA Office of Logic Design rod@klabs.org 915-204-8746

2. Rod’s Second Law • When the manufacturer says “blah blah”, “blah blah” is the law. • Manufacturers don’t write part specs to make the parts hard to use. Circuit Issues for Hitachi-die EEPROMs

3. HN58C1001 Based EEPROMs • Packaged by Austin Semiconductor and Maxwell Semiconductor • Specs flow from HN58C1001 data sheet • Two spec areas are controversial: • Power-up and power-down reset timing • Controversial because it’s hard to meet • Reset Iih • Controversial because few believe the spec • Most of this presentation comes from the Hitachi HN58C1001 data sheet Circuit Issues for Hitachi-die EEPROMs

4. Power-up Reset Timing Reset protect time trp=100 usec min i.e., don’t try to write until 100 usec after power-up • WE* controlled write. CE* controlled spec references \CE* Reset high time tres=1 usec min Circuit Issues for Hitachi-die EEPROMs

5. Reset Timing Details • Be aware of what Vh, Vil, Vccmin are Trp starts when RES* >= Vh Must have RES* <= Vil until Vcc >= Vccmin Circuit Issues for Hitachi-die EEPROMs

6. RES* Voltage Levels • Note Vh! Circuit Issues for Hitachi-die EEPROMs

7. Power-up and -down • i.e., assert RES* during power up and power down Must have RES*<Vil before Vcc>1.0V and asserted until Vcc>=Vccmin Must have RES*<Vil before Vcc<Vccmin and asserted until Vcc<1.0V Circuit Issues for Hitachi-die EEPROMs

8. Noise on Power-up and -down • Assert RES* on power up and power down to avoid data corruption! Noise such as this Actel SX-S FPGA power-up output glitch, if connected to an EEPROM control pin, From klabs.org Circuit Issues for Hitachi-die EEPROMs

9. Control Line Noise Suppression • 20 nsec suppression is not going to help on power-up or -down Circuit Issues for Hitachi-die EEPROMs

10. RES* and WE*/CE* • RES* asserted too early could corrupt write Circuit Issues for Hitachi-die EEPROMs

11. Info from Austin Semiconductor • Results of a discussion with Jeff Kenziorski of ASI about 2/17/2004 • Reset should be low 1 usec before Vcc falls below 4.5V (Vcc min). • The parts will operate at low voltage, like 2.5V • The charge pump might start getting going around Vcc=1V. • To prevent spurious writes on power up, reset should be asserted at least by 1V • By the same reasoning, hold reset asserted during power down until Vcc falls to less than 1V. Circuit Issues for Hitachi-die EEPROMs

12. Further Considerations • The specs must be met under all conditions, not just intentional power-up and power-down: • Brown-outs • Unintentional power-down • Unexpected resets • Use software data protection • Will at least protect against errant software Circuit Issues for Hitachi-die EEPROMs

13. Reset Iih • Spec is controversial! Circuit Issues for Hitachi-die EEPROMs

14. RES* Iih Controversy • Numerous groups report measuring RES* Iih to be < 1 uA and thus reject Hitachi spec as being erroneous • ASI, based on their own measurements, reduced their Iih spec from 100 uA to 10 uA. • BAE reported problems on RAD6000s whose users did not meet the Hitachi spec. • NOTE: Some multi-die packages buffer RES*, so check your data sheet Circuit Issues for Hitachi-die EEPROMs

15. Email from a Project “On our xxx board I measured 5.03 V at the power pin of the reset circuit, 4.95 V at its RESET* output pin, but only 2.56 V at the output of the divider. This set of data implies a fairly low output impedance for the reset circuit of 0.24 K, but a high total input leakage current to the 6 EEPROMs of 215 uA. The average input current is then 36 uA, which is considerably higher than the proposed 10 uA number, but well within the original 100uA spec. While I doubt that we recorded the original value of our divider output, we did measure the value and observe the signal on the oscilloscope. We would definitely not have been satisfied with the presently observed value and therefore must assume that there has been some growth in the leakage.” That’s interesting! Circuit Issues for Hitachi-die EEPROMs

16. He goes on… “For the last few weeks we have been using the new s/w in SEP central that computes a checksum for each EEPROM bank at boot time. The checksum is a 24 bit number that is a sum over all the 24 bit numbers (128K of them) in a given bank. It turns out that unprogrammed EEPROMs show a checksum of $FE0000, which is expected when all bits are set. For one of our flight units, for which I had not yet copied code from one bank to the other, we saw the $FE0000 on several boot occasions. However, at some point the checksum changed to $FE0001. There was no further investigation and meanwhile that bank was overwritten. This is the only case, so far, of a documented bit flip since we installed the checksum s/w. We will continue to track bit flips. (Perhaps the bit flip was related to a low RESET* voltage ??)” Bit flips continue to be a mystery problem! Who knows what will happen if you don’t meet a spec! Circuit Issues for Hitachi-die EEPROMs

17. Conclusion • Not much is known about the internal operation of the Hitachi part • The specs might not make sense, but they still should be adhered to • Design review experience shows these specs are often ignored • Ignore specs at your own risk!! Circuit Issues for Hitachi-die EEPROMs