2004 ITRS Test Chapter

1. 2004 ITRS Test Chapter July 2004 Mike Rodgers Test ITWG Co-chair Intel Corporation

2. Acknowledgements • ITWG Members • Rochit Rajsuman (Advantest), Yi Cai (Agere), Bill Ortner (Agere), Rob Aitken (Artisan), Atul Goel (Agilent), Peter Maxwell (Agilent), Bernd Koenemann (Cadence), Anne Gattiker (IBM), Phil Nigh (IBM), Fred Taber (IBM), Jody Van Horn (IBM), Don Wheater (IBM), Peter Muhmenthaler (Infineon), Phil Burlison (Inoys), Roger Barth (Intel), Don Edenfeld (Intel), Mike Rodgers (Intel), Chad Wren (Intel), Yasumasa Nishimura (Renesas), Jay Bedsole (Motorola), Paul Roddy (Motorola), Don Van Overloop (Motorola), Toshinobu Ono (NEC), Burnie West (NPTest), Bill Price (Philips), Rene Segers (Philips), Tom Williams (Synopsys), Lee Song (Teradyne), Yervant Zorian (Virage) • Contributors • Davide Appello (ST Microelectronics), John Johnson (Intel), John Matthias (Agere), Lynn Schmidt (Agilent), Marc Loranger (Credence), Michael Lee (TSMC), Rudy Garcia (NPTest), Bernd Laquai (Agilent), Sunil Jain (Intel), Udaya Natarajan (Intel), Mike Green (Motorola), Charles Ross (Motorola), John Ferrario (IBM), Dennis Eaton (Agilent), Paul Nesrsta (Rel Inc), Rich Karr (TI), Jim Rhodes (Unisys), Ichiro Fujishiro (Yamaichi), Gordon Cowan (High Rel), Ken Heiman (MCC), Dave Noddin (3M), Herve Deshayes (ST Micro), Dick McClelland (Philips), Carl Buck (Aehr Test), Rafiq Hussain (AMD), Dan Weinstein (Intel), Bob Totorica (Micron), Bob Zacharis (Pycon), John Hartstein (Wells-CTI), Takashi Aikyo, Kenichi Anzou, Kouichi Eguchi, Satoshi Fukumoto, Kazumi Hatayama, Toshinori Inoshita, Shinji Mori, Mitsuyasu Ohta, Akira Ooishi, Masayuki Sato, Hidefumi Toda, Masanori Ushikubo, Osamu Yamada, Chip Cotton (Intel), Dan Sech (Intel), Brett Casey (Intel), Sematech Product Analysis Forum (Larry Wagner (IT), Dave Vallett (IBM)), Stefan Eichenberger (Philips), Ted Lundquist (NPtest), HankWalker (TX A&M), Bob Madge (LSI Logic), Camelia Hora (Philips Research), Maurice Lousberg (Philips Research) Many Thanks!

3. 2004 ITRS Test Chapter Update • High-level test trends remain unchanged from 2001 roadmap revision • High speed interfaces are appearing in a broad range of applications in many market segments • SOC and SIP dominate new designs • Low cost, targeted test platforms emerging • 2004 Update contains only minor changes • Minor adjustments to improve accuracy • Complete annual data for long-term tables

4. Roadmap Plans • 2004 Update • Minor changes to most tables • Completion of long-term table annualization • 2005 Revision • TWG structural changes • Addition of reliability potential solutions • Merge of logic tables • Increased focus on analog/RF table, potential introduction of power device requirements • Merge embedded memory with SOC • Addition of EDA DFT tools, test content, and DFx content • Consolidation of fault models and DFx from SOC section • Addition of test & burn-in sockets and test interface boards

5. 2003 Difficult Challenges Remain • High Speed Device Interfaces • Highly Integrated Designs (SOCs, & SIPs) • Reliability Screens • Manufacturing Test Cost Reduction • Failure Analysis and Diagnosis • Automated Test Program Generation (not ATPG!) • Modeling and Simulation Ad hoc solutions emerging as interim solutions to delay the red brick walls

6. Difficult Challenges High Integration Designs Reliability Screens Test Development Manufacturing Process Management Manufacturing Test Cost Potential Yield Losses Test and Yield Learning Test Technology Requirements Logic Analog Memory System on Chip Reliability Technology Requirements Burn-In Requirements IDDQ Testing Test Handler and Prober Technology Requirements Device Interface Technology Requirements Probe Cards Sockets Modeling and Simulation Potential Solutions Proposed 2005 Chapter

7. Reliability Screens Run Out of Gas • Critical need for development of new techniques for acceleration of latent defects • Burn-in methods limited by thermal runaway • Lowered use voltages limits voltage stress opportunity • Difficulty of determining Iddq signal versus “normal” leakage current noise • New materials • Rate of introduction increasing: Cu, low k, high k, SiGe • Critical interactions of new materials increasing (Cu / low k) • Increasing mechanical and thermal sensitivities

8. High Speed Serial Interfaces • Penetration of high speed interfaces continues to grow • Leading edge data rate trend slowing, but port count trends increasing • Multi-Gbps links dropping into many new product segments • Loopback alone may not be sufficient to achieve needed product quality

9. Analog and RF • Analog and RF circuits becoming pervasive • Penetration increasing in traditionally digital designs • Circuit performance envelope increasing • Test method innovation required • Primary test solutions continue to be based on expensive functional and parametric methods • A relatively little DFT has been developed, and what does exist lacks industry momentum • ITRS Test ITWG needs increased participation in the analog/RF trends and requirements discussion!

10. SOC and SIP • Customer requirements for form factor and power consumption are driving a significant increase in design integration levels • Test complexity will increase dramatically with the combination of different classes of circuits on single die or within a single package • Disciplined, structured DFT is a requirement to reduce test complexity, considerations differ between SOC and SIP • SIP increases focus on KGD and sub-assembly test to reduce costs driven by yield loss • The scope of requirements is growing with integration of new device types such as MEMS, sensors, etc • Cost effectiveness of test becomes a growing challenge for these designs • SIP physical FA is much more difficult, software based test diagnostics will be critical

11. Automated Test Program Generation • Tools for ATE software and test program generation are needed to decrease test development effort and improve time to market • Automated design to manufacturing test program flow • Correct by construction (pre-silicon) • Interoperability standards (STIL, CTL, etc) • Enable test content portability among test platforms • ATE S/W operating environment standards • Direct impact on time to market and product development cost • Driven by product complexity and shorter product cycles

12. The Overall Cost of Test $ NRE Costs $ DFT design and validation $ Test development $ Device Costs $ Die area increase $ Yield loss $ Work-Cell Cost $ Building Capital $ People $ Consumables $ Loadboards, DUT interface $ Capital Equipment Depreciation of: $ Test Equipment $ Handler/Prober Work-Cell Good Units Shipped Untested Units • Goal is to optimize product cost • Must strike a balance between cost of design, manufacture, and test UPH/$M Effectiveness Measure Rejected Units

13. Summary • Interim solutions emerging for difficult challenges, but fundamental issues remain • Chapter focus moving to difficult challenges and potential solutions, away from evolutionary trending • Analog/RF • SIP/SOC • High Speed I/O • Reliability Screens