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SEU Test Bench Status Overview

This article provides an overview of the SEU Test Bench setup, modifications, connectors, and components used for testing SEUV1, SEUV2, and SEUV3 chips. It includes details on lab setup, software, signal types, and future improvements until April 2010.

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SEU Test Bench Status Overview

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  1. Overview & status of SEU Test Bench

  2. Test bench_V1 • Set up first test bench irradiation area Control room LabWindows software « Front board » « Back board » Single ended signals • PCIMCIA “DAQCard-6533” LVDS signals ~5 meters ~20 meters Sample in beam “SEUV1” « Front board »: -Translate -1°) 5V to 3.3V TTL -2°) 3.3V LVDS RxTx «Back board »: - Translate - 1°) 3.3V LVDS RxTx - 2°) 3.3V to 1.5V TTL - 3°) RC impedance adaptation Components used: -DS90LV032A: LVDS Receiver -DS90LV047A: LVDS Driver -74ALVC164245 Voltage translator (“Front board”) -AVC16T245Voltage translator (“Back board”)

  3. Test bench_V2 (1/2) • Set up of the 2nd test bench • Add • current supply control • VDD power supply to separate VDD for linear transistors • and VDD for enclosed transistors • (need to separate pin 63 64 to insert an another VDD) Packaged in TQFP48 and JLCC44 Back board modified

  4. Test bench_V2 (2/2) • Pinout connectors “Back board” 64 PTS HE 10 Connector SUBD37pts VDDIO (*) 14 LVDS Data signals 8 LVDS Command signals Power distribution Translator control signal (*): test bench V2 modifications Pin 63 VDDIO Pin 64 for 1.5V VDD1

  5. TTL LVDS Test bench_V3 irradiation area Control room • Set up • Frequency used up to 40MHz • Synchronize with a signal machine • “mezza board” has been foreseen to work without “back board” and directly connected to a sample with Bonn LVDS drivers. (need a modification to work with “Back board”) LabWindows for USB interface Quartus for FPGA «DE2 board» «mezza_DE2» « Back board » Single ended signals LVDS signals USB link ~20 meters ~5 meters Sample in beam “SEUV2”& “SEUV3” External trigger TTL signal from cycle machine

  6. FEx4 test bench • Set up • Possibility to switch between SEU and analog test. • Compatible with SEU test bench V1 setup if we use an external translator (9 inputs, 2 outputs). • Additional analog signal to drive FEx4 analog part LabWindows SEU Test « Front board » « Back board » Single ended signals “DAQCard-6533” LVDS signals Visual C++ Analog Test USB ~5 meters ~20 meters NI USB-6008 Sample in beam “FEx4” Translator 5V/1.5V GPIB Current source Pulse generator ~2 mètres BNC BNC

  7. Future • Open discuss of modifications and improvements to take the best way until april 2010 • Powering system • Actually we use 7 power supplies • ( 14 independent outputs with regulation) • Do we dedicate DE2 board for SEU chip and analog tests set up for FEx4 chip? • Implement analog tests inside DE2 board can take more time • Each chip have its own test bench • Need to implement SEU test functions inside the analog set up to test FEx4’s latches • Check all interfaces for compatibility and to improve the robustness. Set up in control room

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