EE534 VLSI Design System summer 2004 Lecture 14:Chapter 10 Semiconductors memories

1. EE534VLSI Design Systemsummer 2004 Lecture 14:Chapter 10Semiconductors memories

2. Chapter 10: SEMICONDUCTOR MEMORIES • Memory classification (more history than technical) • Memory architecture and basic operations • The memory core (data storage units) • Peripheral circuits (decorder, sens-amp, etc.) • Reliability concerns (processing and operational) • General design considerations and future trends

3. Feynman’s Prediction in 1959 • To store Encyclopedia Britannica on the head of a pin (10-2 inch square), we need a dot every 8nm • To store all books in history (around 25 million copies, which needs 1015 bits, or peta-bit) with 8nm in 2D, we need just a few square yards. • If we code the text part and do 3D storage of (55 5 atoms), all books in history will be smaller than the sand dust (now you are talking about smart dust). • There is NO physical principles that prohibit this.

4. Far Away from the End... “What I have demonstrated is that there is room---that you can decrease the size of things in a practical way. I now want to show that there is plenty of room. I will not now discuss how we are going to do it, but only what is possible in principle---in other words, what is possible according to the laws of physics. I am not inventing anti-gravity, which is possible someday only if the laws are not what we think. I am telling you what could be done if the laws are what we think; we are not doing it simply because we haven't yet gotten around to it.” (Richard P. Feynman, There is plenty of room at the bottom, Dec. 1959)

5. A Word on Terminology for Semiconductor Memories • Different unit to consider in design • circuit designers: bits • chip designers: bytes (8 or 9 bits), gigabyte (109 bytes), terabyte (1012), peta bytes (1015), exa bytes (1018), googol bytes (10100). • system designers: words (32 bits now, but many 64-bit system appearing) • ROM (read-only memory), RAM (random-access memory), EEPROM (electrically erasable programmable read-only memory), etc. can take better names • SDRAM (synchronous dynamic RAM), etc. • off-chip access, embedded SRAM, etc.

6. Semiconductor Memory Classification FIFO: First-in-first-out LIFO: Last-in-first-out (stack) CAM: Content addressable memory

7. Growth in DRAM Chip Capacity

8. Memory Architecture: Decoders pitch matched line too long

9. 2D Memory Architecture bit line 2k-j word line Aj Aj+1 Row Address storage (RAM) cell Row Decoder Ak-1 m2j Column Address A0 selects appropriate word from memory row A1 Column Decoder Aj-1 Sense Amplifiers amplifies bit line swing Read/Write Circuits Input/Output (m bits)

10. 3D Memory Architecture Row Addr Column Addr Block Addr Input/Output (m bits) Advantages: 1. Shorter word and/or bit lines 2. Block addr activates only 1 block saving power

11. Hierarchical Memory Architecture Row Address Column Address Block Address Global Data Bus Control Block Selector Global Amplifier/Driver Circuitry I/O • Advantages: • shorter wires within blocks • block address activates only 1 block: power management

12. Read-Write Memories (RAM) • Static (SRAM) • Data stored as long as supply is applied • Large (6 transistors per cell) • Fast • Differential signal (more reliable) • Dynamic (DRAM) • Periodic refresh required • Small (1-3 transistors per cell) but slower • Single ended (unless using dummy cell to generate differential signals)

13. Three Transistors DRAM cell ●Binary information is stored in the from of charge in the capacitor C1 ●M2 is storage transistor ●Pass transistors act as access switches for data read and write operation ●All data read and data write operation are performed when PC is low. Reads are non-destructive No constraints on device ratios Value stored at X when writing a “1”=VWWL-VTn

14. Write ‘1’ and read ‘1’ operation Write operation ●During write operation signal WS is high As a result M1 is turned on and allow charge sharing between C2 and C1., which turned on M2. ●During read operation: M1 is off RS is high, M3 is on and consequently C3 discharge through M2 and M3. Low level on Dout (C3) is the finger print of stored “1” Read operation

15. Write ‘0’ and read ‘0’ operation For write “0” operation: WS is high, M1 turn on C1 and C2 discharge through M1 M2 turned off because of low voltage level of C1. During read “0” operation RS is high M3 turn on but M2 is off C3 remains high High level on Dout is the finger print of stored “0” bit.

16. 3-T DRAM cell during operation

17. 1-Transistor DRAM Cell BL WL Write "1" Read "1" WL M 1 X C V - V S GND T small perturbation DD V DD BL VDD/2 V /2 VDD/2 DD C sensing BL Write: C is charged or discharged by asserting WL and BL. S Read: Charge redistribution takes places between bit line and storage capacitance, The direction of which determines the value of data stored. C S VDD/2 ------------------------ D V = – V = BL PRE C + C S BL Voltage swing is small; typically around 250 mV.

18. DRAM Cell Observations • DRAM cells are single ended in contrast with SRAM cells • Read-out of 1T DRAM is destructive (3T is not), and refresh is necessary after read. • 1T DRAM needs an explicit capacitance (3T needs not) • 1T DRAM requires a sense amp for each bit line, due to charge redistribution read-out • When writing 1’s into DRAM cells, a Vth is lost. This charge loss can be circumvented by bootstrapping the word line (not the bit line) to a higher value than VDD.

19. Read-Write Memories (RAM) • Static (SRAM) • Data stored as long as supply is applied • Large (6 transistors per cell) • Fast • Differential signal (more reliable) • Dynamic (DRAM) • Periodic refresh required • Small (1-3 transistors per cell) but slower • Single ended (unless using dummy cell to generate differential signals)

20. 6-transistor SRAM Cell WL M2 M4 Q M6 M5 Q M1 M3 !BL BL Note that it is identical to the register cell from static sequential circuit - cross-coupled inverters Consumes power only when switching - no standby power (other than leakage) is consumed The major job of the pullups is to replenish loss due to leakage Sizing of the transistors is critical!

21. SRAM Cell Analysis (Read) WL=1 M4 M6 Q=0 M5 Q=1 M1 Cbit Cbit BL=1 BL=1 Read-disturb (read-upset): must carefully limit the allowed voltage rise on Q to a value that prevents the read-upset condition from occurring while simultaneously maintaining acceptable circuit speed and area constraints

22. SRAM Cell Analysis (Read) WL=1 M4 M6 Q=0 M5 Q=1 M1 Cbit Cbit BL=1 BL=1 Cell Ratio (CR) = (WM1/LM1)/(WM5/LM5) VQ = [(Vdd - VTn)(1 + CR (CR(1 + CR))]/(1 + CR) To avoid read-disturb, the voltage on node Q should remain below the trip point of the inverter pair for all process, noise, and operating conditions.

23. Read Voltages Ratios Vdd = 2.5V VTn = 0.5V The voltage rise inside the cell will not rise above the threshold if Cr>1.2

24. SRAM Cell Analysis (Write) WL=1 State shown is that before write takes effect (1 is stored, trying to write a 0) M4 M6 Q=0 Q=1 M5 M1 BL=1 BL=0 Pullup Ratio (PR) = (WM4/LM4)/(WM6/LM6) VQ = (Vdd - VTn) ((Vdd – VTn)2 – (p/n)(PR)((Vdd – VTn - VTp)2) In order to write the cell, the pass gate M6 must be more conductive than the M4 to allow node Q to be pulled to a value low enough for the inverter pair (M2/M1) to begin amplifying the new data. The maximum ratio of the pullup size to that of the pass gate required to guarantee that the cell is writable – M6 in linear, M4 in saturation

25. Write Voltages Ratios Vdd = 2.5V |VTp| = 0.5V p/n = 0.5

26. Design Issues: Cell Sizing • Keeping cell size minimized is critical for large caches • Minimum sized pull down fets (M1 and M3) • Requires minimum width and longer than minimum channel length pass transistors (M5 and M6) to ensure proper CR • But sizing of the pass transistors increases capacitive load on the word lines and limits the current discharged on the bit lines both of which can adversely affect the speed of the read cycle • Minimum width and length pass transistors • Boost the width of the pull downs (M1 and M3) • Reduces the loading on the word lines and increases the storage capacitance in the cell – both are good! – but cell size may be slightly larger

27. 6T-SRAM — Layout • Actually all transistors in 6-T SRAM cell can be minimum-sized regardless of the writability concerns, as long as the differential signal is maintained (one side will be able to write in, and then the bi-stability takes over) • The bit lines are usually pre-charged to VDD/2 instead of VDD to take full advantage of the differential signal. VDD M2 M4 Q Q M1 M3 GND M5 M6 WL BL BL

28. Resistance-load SRAM Cell

29. 1 0 1 1 0 1 1 0 1 0 1 0 W0: 1011 W1: 0110 W2: 1010 W3: 1111 1 1 1 1 MOS NOR ROM Logic 1 bit is stored as a the absence of an active transistor While a logic 0 bit is stored as the presence of an active transitor. In actual ROM layout 1 bit is programmed by omitting the drain or source connection 0 bit is programmed by connecting the drain to the ground or metal to diffusion contact

30. Erasable Programmable ROM(EPROM): Floating-gate transistor (FGMOS)

31. Floating-Gate Transistor Programming: EPROM • Hot-carrier injection is self-limiting: no detailed control circuitry necessary • Writing and sensing on the same transistor: simplified • Erase by UV may have residual effects Virtually all nonvolatile memories are currently based on the floating gate approach.

32. Floating gate tunneling oxide (FLOTOX): EEPROM • F-N tunneling is not as self-limiting, and read/write need to be carefully controlled. • Vth variation is large: one more control transistor • Other geometry possible (split-gate, etc.)

33. Floating-gate transistor (FGMOS) :Flash Memory • Hot-carrier injection write operation (self-limiting) • Block erase by F-N tunneling with careful tuning on the block level • Sensing by the same transistor (small cell footprint)

34. Cross-sections of NVM cells Flash EPROM Courtesy Intel

35. Characteristics of State-of-the-art NVM

36. Next Lecture and Reminders • Next lecture • Project report due on 1st December • Project oral exam: 1st December full adder group.