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MICE Readout DFPGA Firmware Progress

MICE Readout DFPGA Firmware Progress. Done  Trip-t  DFPGA  AFPGA Discriminator bit map transfer control blocks done and simulated Reading Trip-t Discriminator Bit map into DFPGA MapFIFOs with Depth control

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MICE Readout DFPGA Firmware Progress

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  1. MICE Readout DFPGA Firmware Progress Done  Trip-t  DFPGA  AFPGA Discriminator bit map transfer control blocks done and simulated Reading Trip-t Discriminator Bit map into DFPGA MapFIFOs with Depth control Down loading the Discriminator Bit map into D-A interface FIFO on Digitise Underway  Add Xilinx Core Generated components Simulate Next  Add pin configuration Simulate  Test  Implement L1 Data Readout

  2. Trip-t Interface MapFIFO0UMSB MapFIFO0ULSB Disc 0 map 16 bit MapFIFO0LMSB MapFIFO0LLSB D-A FPGA Interface DIGEN0[ U/L/B] PRE-RST M U X Trip-t Interface MODE CTRL TxFIFO-D 8 bit 8 ->1 Read Select U/L Write DIGEN1[ U/L/B] MapFIFO1UMSB MapFIFO1ULSB Disc 1 map 16 bit MapFIFO1LMSB MapFIFO1LLSB

  3. Trip-t Signals

  4. DFPGA control signals

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