ECE 353 Introduction to Microprocessor Systems

1. ECE 353Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 3

2. Topics • Code Generation and Debugging Tools • ARM7TDMI Microprocessor • Organization • Programming

3. Code Generation • Programming Language Characteristics • High-Level Language (HLL) • Assembly Language • Machine Language • Assembler Functions • What does an assembler do?

4. Assembly Language • Assembler Types • Native assembler • Cross-assembler • General Instruction Syntax • Label • Mnemonic • Operands • Comments • Key ARM Assembler Directives

5. Code Generation Process –Generic

6. Code Generation Process –ECE 353andECE 315

7. Hardwarefor Sample Program

8. Source Code File ; Filename: sample.s ; Author: ECE 353 Staff ; Description: sample program for week 3 lecture ; do **NOT** use this as the basis for any programming! EXPORT Reset_Handler ;make available to linker IOPORT_ADDRESS EQU 0x80001000 AREA Reset, CODE, READONLY ARM Reset_Handler LDR PC, aLoop ;jump absolute Loop LDR R0, aPort ;load address of port LDR R1, [R0] ;read switch state LSL R1, #8 ;shift left 8 bits to align MVN R1, R1 ;complement STR R1, [R0] ;write LEDs NOP ;do nothing B Loop ;repeat forever aLoop DCD Loop aPort DCD IOPORT_ADDRESS END

9. Assembler Listing File (1) 4 00000000 ; do **NOT** use this as the basis for any programming! 5 00000000 6 00000000 EXPORT Reset_Handler ;make available t o linker 7 00000000 8 00000000 80001000 IOPORT_ADDRESS EQU 0x80001000 9 00000000 10 00000000 AREA Reset, CODE, READONLY 11 00000000 ARM 12 00000000 13 00000000 Reset_Handler 14 00000000 E59FF018 LDR PC, aLoop 15 00000004 Loop 16 00000004 E59F0018 LDR R0, aPort ;load address of port 17 00000008 E5901000 LDR R1, [R0] ;read switch state 18 0000000C E1A01401 LSL R1, #8 ;shift left 8 bits to align 19 00000010 E1E01001 MVN R1, R1 ;complement 20 00000014 E5801000 STR R1, [R0] ;write LEDs 21 00000018 E1A00000 NOP ;do nothing 22 0000001C EAFFFFF8 B Loop ;repeat forever 23 00000020 24 00000020 00000000 aLoop DCD Loop 25 00000024 80001000 aPort DCD IOPORT_ADDRESS 26 00000028 27 00000028 END

10. Assembler Listing File (2) Command Line: --debug --xref --device=DARMAD --apcs=interwork -osample.o -IC:\K eil\ARM\INC\ADI --list=sample.lst sample.s ARM Macro Assembler Page 1 Alphabetic symbol ordering Relocatable symbols Loop 00000004 Symbol: Loop Definitions At line 15 in file sample.s Uses At line 22 in file sample.s At line 24 in file sample.s Reset 00000000 Symbol: Reset Definitions At line 10 in file sample.s Uses None Comment: Reset unused Reset_Handler 00000000 Symbol: Reset_Handler Definitions At line 13 in file sample.s Uses At line 6 in file sample.s Comment: Reset_Handler used once

11. Assembler Listing File (3) Symbol: aLoop Definitions At line 24 in file sample.s Uses At line 14 in file sample.s Comment: aLoop used once aPort 00000024 Symbol: aPort Definitions At line 25 in file sample.s Uses At line 16 in file sample.s Comment: aPort used once 5 symbols ARM Macro Assembler Page 1 Alphabetic symbol ordering Absolute symbols IOPORT_ADDRESS 80001000 Symbol: IOPORT_ADDRESS Definitions At line 8 in file sample.s Uses At line 25 in file sample.s Comment: IOPORT_ADDRESS used once 1 symbol 321 symbols in table

12. Disassembly Window 0x00080000 E59FF018 DD 0xE59FF018 0x00080004 E59F0018 LDR R0,[PC,#0x0018] 0x00080008 E5901000 LDR R1,[R0] 0x0008000C E1A01401 MOV R1,R1,LSL #8 0x00080010 E1E01001 MVN R1,R1 0x00080014 E5801000 STR R1,[R0] 0x00080018 E1A00000 NOP 0x0008001C EAFFFFF8 B 0x00080004 0x00080020 00080004 DD 0x00080004 0x00080024 80001000 ANDHI R1,R0,R0 0x00080028 00000000 ANDEQ R0,R0,R0 0x0008002C 00000000 ANDEQ R0,R0,R0 0x00080030 00000000 ANDEQ R0,R0,R0 0x00080034 00000000 ANDEQ R0,R0,R0 aLoop aPort B/BL{<cond>} <target_address> RTL: PC  PC + (signed_immediate_24 << 2)

13. Linker Map File (1) ARM Linker, RVCT3.0 [Build 942] for uVision [Evaluation] ================================================================================ Section Cross References ================================================================================ Image Symbol Table Local Symbols Symbol Name Value Ov Type Size Object(Section) sample.s 0x00000000 Number 0 sample.o ABSOLUTE Reset 0x00080000 Section 40 sample.o(Reset) Loop 0x00080004 ARM Code 0 sample.o(Reset) Global Symbols Symbol Name Value Ov Type Size Object(Section) BuildAttributes$$THUMB_ISAv1$ARM_ISAv4$M$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE Reset_Handler 0x00080000 ARM Code 0 sample.o(Reset) ================================================================================ Memory Map of the image Image Entry point : 0x00080000 Load Region LR_1 (Base: 0x00080000, Size: 0x00000028, Max: 0xffffffff, ABSOLUTE) Execution Region ER_RO (Base: 0x00080000, Size: 0x00000028, Max: 0xffffffff, ABSOLUTE) Base Addr Size Type Attr Idx E Section Name Object 0x00080000 0x00000028 Code RO 1 * Reset sample.o Execution Region ER_RW (Base: 0x00010000, Size: 0x00000000, Max: 0xffffffff, ABSOLUTE) **** No section assigned to this execution region **** Execution Region ER_ZI (Base: 0x00010000, Size: 0x00000000, Max: 0xffffffff, ABSOLUTE) **** No section assigned to this execution region ****

14. Linker Map File (2) Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug Object Name 40 8 0 0 0 244 sample.o ------------------------------------------------------------------------ 40 8 0 0 0 244 Object Totals 0 0 0 0 0 0 (incl. Generated) 0 0 0 0 0 0 (incl. Padding) ------------------------------------------------------------------------ 0 0 0 0 0 0 Library Totals 0 0 0 0 0 0 (incl. Padding) ------------------------------------------------------------------------ ================================================================================ Code (inc. data) RO Data RW Data ZI Data Debug 40 8 0 0 0 244 Grand Totals 40 8 0 0 0 244 Image Totals ================================================================================ Total RO Size (Code + RO Data) 40 ( 0.04kB) Total RW Size (RW Data + ZI Data) 0 ( 0.00kB) Total ROM Size (Code + RO Data + RW Data) 40 ( 0.04kB) ================================================================================

15. Hex Record Format :0400000500080000EF :020000040008F2 :1000000018F09FE518009FE5001090E50114A0E1AD :100010000110E0E1001080E50000A0E1F8FFFFEA38 :0800200004000800001000803C :00000001FF 0x00080000 E59FF018

16. Debugger Basics • So, why is it called debugging, anyway? • Terminology • Testing • Debugging • Types of errors • Symbolic debugging • UUT/DUT • Typical Debugger Capabilities • Display/modify machine state • Load/run/halt • Step-into / step-over • Breakpoints

17. Simulator Runs on a host computer, and simulates execution of your code. No actual hardware required. Strengths Weaknesses

18. Native Debugger • Code is executed on a host computer with a compatible instruction set. • Strengths • Weaknesses

19. Resident Monitor Monitor is a stand-alone program that runs on the UUT, typically communicates over serial interface to a terminal. Strengths Weaknesses

20. Remote Debugger • Similar to resident monitor, but only small debugger kernel on UUT. Main debugger software runs on a host computer connected to the UUT. • Strengths • Weaknesses

21. In-Circuit Emulator (ICE) • Replaces UUT CPU with hardware that gives full control of CPU pins (i.e. can run arbitrary bus cycles). Often contain overlay memory to allow testing of software before system hardware is available. May clamp over existing CPU that is soldered in place. • Strengths • Weaknesses

22. JTAG Emulators • Special serial interface to the device (IEEE 1149.1) • Boundary scan cell • Boundary scan chain • Emulation (internal) scan chain • Background debug support • Strengths • Weaknesses

23. Hardware-Assisted Debug • In microprocessors with on-chip nonvolatile memory (like the ADuC7026), it is not feasible to set software breakpoints • Debug hardware is added to support debugging in these conditions • Code breakpoint registers • Data breakpoint registers • ARM7 combines both of these into a watchpoint register set

24. Code Development Tips • Use structured programming methods • No spaghetti code! • Use descriptive symbols and names • Write comments as you go (or before!) • When fixing assembler errors, fix only the top one or two and re-assemble – a lot of the later errors may be due to the first few • When debugging, verify what the registers are loaded with as compared to what you think (know?) they should be loaded with • Textbook has a good section on debugging

25. ARM7TDMIProcessor Core

26. ARM7 Operating Modes • User • Normal program execution mode • System • For running operating system tasks at user privilege level • Supervisor • Protected mode for operating system • Abort • Used to implement process and/or memory protection • Two classes of aborts – data abort, prefetch abort • Undefined • Supports software emulation of unsupported instructions and unimplemented hardware coprocessors • FIQ • Fast interrupt handling • IRQ • General purpose interrupt handling

27. ARM7 Programmers’ Model • R15-R0 • Sixteen general-purpose registers • Special functions • R15 is the Program Counter (PC) • If R15 is the destination operand, some instructions will exhibit special behavior for mode changes • R14 is the Link Register (LR) • For subroutine calls and interrupts/exceptions, the return address is stored in LR. It must be saved before calls are made in the subroutine. • R13 is used as the Stack Pointer (SP)

28. ARM7 Programmers’ Model (cont) • Current Process Status Register (CPSR) • Condition code flags (N, Z, C, V) • Interrupt disable bits (I, F) • Thumb mode enable (T) • Never change directly! • Operating mode select • Reserved bits • Do not alter the state of these bits for compatibility with future ARM products • I, F and mode cannot be changed in user mode!

29. ARM7 Programmers’ Model (cont) • Suspended Process Status Register (SPSR) • SPSR is only present when the CPU is operating in one of the exception modes • Each exception mode has its own SPSR, since exception handlers may cause other exceptions. • SPSR is a copy of the CPSR immediately before the exception mode was entered. • When returning from the exception, the value in SPSR is used to restore the CPSR to the proper state for the process that was interrupted.

30. ARM7 Register Banking

31. ARM7 Reset • CPSR • Supervisor mode • I & F set (interrupts disabled) • T cleared (ARM mode) • PC is cleared to 0x00000000 and an instruction is fetched • This is the bootstrap instruction • All register values except PC and CPSR are indeterminate

32. ARM7 Reserved Addresses

33. ARM7 Coprocessors • The ARM architecture is designed to support the addition of tightly-coupled hardware coprocessors • System control processor (CP15) • Floating-point coprocessor • Special instructions are used to read/write coprocessor registers • If the coprocessor is not implemented, an undefined instruction exception occurs, permitting software emulation of the coprocessor functions. • The ADuC7026 does not implement any coprocessors

34. ARM7 Condition Codes

35. ARM7 Condition Codes (cont) • Things to remember when using conditions • Signed and unsigned arithmetic require different conditions to get same result • Unsigned HS equivalent to signed GE • The AL (always) condition is implied if no condition mnemonic is used • The meaning of the condition is true if op1 cond op2 • CMP R0, R1 • BLLT subroutine • Subroutine called if R0 is less than R1 (signed)

36. ARM7 Instruction Encoding

37. Wrapping Up • Homework #2 due Wednesday 2/22 • Reading for next week • Chapter 4, 5 • ARMINSTREF • Pre-Quiz #3 on Learn@UW, complete by Monday class time

38. Boundary Scan I/O Cell

39. Boundary Scan Chain

40. Emulation Scan Chain

41. RADM Grace Hopper • References • http://www.arlingtoncemetery.net/ghopper.htm • http://www.history.navy.mil/photos/images/h96000/h96566kc.htm