Device Scaling Leading to Next Generation of Fabrication Techniques

1. Device Scaling Leading to Next Generation of Fabrication Techniques Class Project, ELEG 5213 By Tim Morgan and Sam Mensah

2. What is Scaling?

3. Outline • CMOS Devices • MOSFET • Fabrication Techniques • Scaling • Limitation to existing Fab. Processes • The Next Generation of Device Fabrication • Nanostructure Manipulation

4. MOSFET

5. Types of MOSFET

6. Current Fabrication Process • Resist • Optical Lithography • Resist • Electron beam lithography • Ion implantation • Step and repeat

7. If the dimensions of an object is scaled linearly, how does its properties scale? • Electrical properties • Mechanical properties • Optical properties • Surface area • Mass and weight • Other! • Different properties scale differently • It will be useful to know the scaling laws and how it affects each property

8. In Device Fabrication; • The reduction in size of the geometric dimensions of ICs. i.e. the lateral geometric dimensions and interconnects are reduced • Minimize feature size of gate length, interconnect line width etc • Resulting in an increase in the number of devices in electronic gardgets

9. Moore’s Law

10. Types of Scaling

12. Constant-Voltage scaling & Constant-Field scaling

13. Scaling of MOSFET

14. Constant-voltage scaling • Only lateral dimensions of the MOSFET are scaled. – purely geometrical • What happens as the dimensions shrink? • Leads to high fields in the channel causing dielectric breakdown (avalanche breakdown) • Most parameters changes • No change in drain current was observed • Short channel effects

15. At short gate lengths, FETs have • Threshold voltage shift • Clear pinch-off of the channel • increased leakage current • Increased output conductance

16. Constant-field scaling • Geometrical parts as well as other parameters such as voltage and e-field are scaled

17. Constant-field Scaling

18. Transistor Nanotechnology Research at Intel • Novel device architectures, e.g. Tri Tri-gate • Carbon Nanotubes • Si and Non Non-Si Nanowires • III-V Materials, e.g. InSb • GOALS: • Continue improving device speed/clock frequency • Maintain/reduce power consumption • Further dimensional scaling

19. Proposed by intel

20. Copied from an intel ppt

21. Carbon Nanotubes • Rolled--up graphene sheet(s) • Roll--up vector determines electronic properties of tubes • metallic • semiconducting • Dimensions:11--25nm depending on how they are form

22. Carbon Nanotube Interconnects • Resistance of Metal lines increases as lines are scaled. • Electrons collide with walls of wire causing increase in resistance. • Collisions can damage wire over time Nanotubes • Conduct current in a linear fashion and avoid these collisions: 1 D transport • Able to pass high current without failure: 109 A/cm2 (Cu 106 A/cm2) • Good mechanical stability (strength and toughness); enables other processing (etch/cleans)

23. Conclusions • Moore Moore’s Law is alive and well: CMOS transistors scaling is expected to continue until around 2020, with new architectures such as tri-gate, carbon nanotubes, nanotubes, nanowires and III-V semiconducting materials. • Promising research results in areas such as spintronics, phase change, and optical switches, may provide a path for beyond 2020.