An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement

1. An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement Chin-Lung Su, Yi-Ting Yeh, and Cheng-Wen Wu National Tsing Hua University Hsinchu, Taiwan

2. Introduction • Memory cores are widely used in SOC designs • They have higher density and occupy larger area • Dominate the chip yield • Their use is increasing in nano-technologies according to ITRS • Reliability is also an important issue for memory • ECC and redundancy repair are both widely used fault tolerance techniques • After production test, there may be some un-used redundancy • Combine ECC and un-used redundancy • Higher yield and greater degree of fault tolerance IC-DFN/08-06/cww

3. Chip Area Breakdown Source: International Technology Roadmap for Semiconductors (ITRS), 2001-2005 IC-DFN/08-06/cww

4. RAM Controller Pattern Generator Test Collar (MUX) Comparator Go/No-Go BIST Module RAM Controller Typical RAM BIST Architecture Microprogram Hardwired CPU core IEEE 1149.1 Counter LUT LFSR IC-DFN/08-06/cww

5. Sharing Controller & Sequencer IC-DFN/08-06/cww

6. Single Double 16 16 Corrector Decoder RAM 6 Syndrome Syndrome Gen 16 16 16 6 6 6 Cb Gen Cb Gen Data Bus Typical RAM ECC Architecture Mainly for improving reliability IC-DFN/08-06/cww

7. Reconfiguration Mechanism Redundancy Analyzer RAM MUX Spare Elements BIST I/O RAM Built-In Self-Repair (BISR) Mainly for improving yield IC-DFN/08-06/cww

8. A Power-On BISR Scheme Q D A Main Memory Wrapper MAO BIRA POR BIST Spare Memory MAO: mask address output; POR: power-on reset Source: ITC’03 IC-DFN/08-06/cww

9. Proposed Scheme • Integrated ECC and Redundancy Repair Scheme • Hard errors are repaired by physical redundancy in field • Soft-error correction ability is not harmed by hard errors • Enhance reliability • Assumptions • During Error Identification phase, no other faults may occur • Error rate << system clock speed IC-DFN/08-06/cww

10. Phases of Proposed Scheme IC-DFN/08-06/cww

11. Error Identification Phase • Write back process • Write the corrected data back to memory • Read data from the same address • Soft error may be eliminated with this process • Assume that no other errors may occur • After error identification • “Hard repair phase” for a hard error/fault • “Fault-free phase” for a soft error IC-DFN/08-06/cww

12. Hard Repair Phase • Repair this hard fault with spare • Map the faulty word to redundant word • Write the corrected data into redundant word • Hard fault location • In main memory: follow the above procedure • In redundant memory: mark the faulty redundant element • During this phase, memory cannot be accessed • Idle mode • Hard fault is removed after this phase • Reliability and MTTF is increased IC-DFN/08-06/cww

13. Experimental Results • Technology: TSMC 0.25um CMOS process • The redundant memory consists of eight spare rows and four spare columns IC-DFN/08-06/cww

14. Experimental Results (cont.) !ECC: Without ECC SEC: With SEC/DED ECC SECP: Proposed Scheme Area = Memory + ECC + BIST Cost = Area / MTTF IC-DFN/08-06/cww

15. Reliability Improvement 8K x64 memory r+c = 12 IC-DFN/08-06/cww

16. Conclusions • An integrated ECC and redundancy repair scheme is proposed • Enhancing memory reliability and MTTF • Low area overhead • Integrating ECC Controller with BIST • No timing penalty in normal operation • Cost-effective way for reducing the effect of parametric defects IC-DFN/08-06/cww