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CSE 242A Integrated Circuit Layout Automation

CSE 242A Integrated Circuit Layout Automation. Lecture 5: Placement Winter 2009 Chung-Kuan Cheng. Placement Formulation. ½ perimeter of min bounding box Single trunk (v or h) Spanning tree Steiner tree. Layout Area. Rectilinear Area. Block Shapes.

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CSE 242A Integrated Circuit Layout Automation

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  1. CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng

  2. Placement Formulation ½ perimeter of min bounding box Single trunk (v or h) Spanning tree Steiner tree

  3. Layout Area Rectilinear Area Block Shapes Single row height: width=1~2 or even hunderds Multiple rows Donuts

  4. Formulation: Constraints • Groups: A set of cells to be placed within X & Y distance • Regions: If a cell is attached to a region, it needs to be placed within the specified area. • Sites: Each slot has a type. Each cell is specified by types on its area. The types have to be matched for a correct placement.

  5. IO Placement

  6. Placement Formulation Quadratic Assignment (NP Complete) Linear Assignment

  7. Placement Methods • Analytical Method • Constructive Method • Iterative Method

  8. Analytical Method: QPlace (RAMP) • Resistive Analog Module Placement b a b a c c d d

  9. Analytical Method (Obj)

  10. Analytical Method: Obj

  11. Analytical Method Constraints • Sum xi = c1 • Sum xi2= c2 • Sum xi3= c3 • Sum xin= cn

  12. Repulsive Force If i & j are not connected j i By density

  13. Constructive Method Input: Seeds X, Unplaced set V-X Pick a cell in in V-X with strongest connection to X Place i at a location so that partial cost is minimized Adv: Fast, Simple, Flexible Dis: Quality of the Results

  14. Iterative Improvement • Given an initial placement • A. Find the best pair to swap • B. Find the best sequence to swap D A A B C B C D

  15. Iterative Method Target zone of each component i: Count from left. Each ae or be is counted once, Target zone = Region between |N| and |N|+1.

  16. Simulated Annealing

  17. SA Cost Function

  18. Window Size, Temperature, & acceptance ratio

  19. Local Placement a b c d Choose k cells Find the opt sequence of the k cells Find a larger set of cells Derive the opt matching (Ignore the relation between the k cells)

  20. Performance Driven Placement Replication a a x x x b b Gate Sizing, Buffer Insertion

  21. Pin Swapping a b c a c b

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