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CSE 242A Integrated Circuit Layout Automation

CSE 242A Integrated Circuit Layout Automation. Lecture: Global Routing Winter 2009 Chung-Kuan Cheng. Outline. Menu Multi-Commodity Flow Top-Down Approach Steiner Tree. Global Routing Menu. Global Routing MCF. LP & Duality. Net Ordering. Global Routing Top-Down Approach. P2. P1. 4.

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CSE 242A Integrated Circuit Layout Automation

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  1. CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng

  2. Outline • Menu • Multi-Commodity Flow • Top-Down Approach • Steiner Tree

  3. Global Routing Menu

  4. Global Routing MCF • LP & Duality

  5. Net Ordering

  6. Global RoutingTop-Down Approach

  7. P2 P1 4 T(1)…T(4) P1 P2 2 T(5)…T(6) P3 P1 P2 4 P4 P3 T(7)…T(10) P1 P2 1 T(11)

  8. Linear Programming V1 H1 H2 V2

  9. Steiner tree

  10. Maze Routing • Breadth First Search: • Map memory reduction 1 2 1 1 2 2 2 1 1 2 2 1 1 2 2 1 1 1 2 2 1 1 S 1 1 1 2 2 1 1 1 1 2 2 1 2 2 1 2 2 2 1 2 1 1 3 1 1 3 2 3 1 1 3 2 1 2 1 3 2 1 S 1 1 3 2 1 2 1 3 2 3 1 1 3 1 1 A sequence that guarantees the predecessor is different from its successor. # states: 1, 2, Empty, Filled, 1, 2, 3

  11. Speed-up • Limit to a bounding box * 120% • Start from two ends • Expand from the corners farthest from the center • Expand the frontier closer to the target first t s

  12. Depth First Search 5 4 Line probe 3 3 2 4 1 2

  13. A* router t i s

  14. Ripup and Reroute B • Net sequence ordering • Penalty function on overlapping • Route around existing wires • Plowing or compaction • Topological routing C A

  15. Ripup and reroute with cost driven router

  16. Overlap Model

  17. 6 7 8 1 2 3 4 5 5 4 7 1 3 2 6 8

  18. Hybrid Router

  19. River Routing • Net Ordering • For each pin (circular order) • If it is a starting pin, push • Else if is ending pin, pop into a queue. • Route nets to follow contour 3 2 4 6 6 5 5 4 2 3

  20. Planar Routing • Power & Ground Distribution • Find a cut line that separates the chip into two regions • Obj: min tree length P + treelength G P G G P P G

  21. Gate Matrix Vdd A 1 3 B 4 A B 2 5 Z B A 9 8 A 6 7 10 B

  22. 2 1 4 5 3 7 6 9 10 8 Z C A B

  23. Cell Generation Vdd Vdd B A A B C C D Z Z D Z A D C C D A B B

  24. Vdd 3 A B A B 4 4 3 C C 2 2 Z D 1 1 D Z

  25. Find an Euler path on graph G & its dual with same sequence of labels • Given serial & parallel graph, the operation is commutative 1 1 1 2 2 2 3 2 1 3

  26. Compaction 1 1 2 3 4 5 9 ‘ 7 8 6 t S

  27. Compaction with Wire Jogging

  28. Compression ridge 45 degree path

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