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ITRS Roadmap for Lower Power Design

Understand the ITRS roadmap for lower power design, including scaling factors, interconnect power reduction methods, and clock gating. Learn how gate, drain, source scaling impacts capacitance, voltage, and frequency.

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ITRS Roadmap for Lower Power Design

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  1. CSE 252A Integrated Circuit Layout Automation Lecture 2: ITRS Roadmap and Lower Power Design Methodology Winter 2009 Chung-Kuan Cheng

  2. Agenda • Scaling • ITRS Roadmap

  3. Scaling -- Gate Drain Scaling Factor is S Drain Gate Source Source

  4. Scaling -- Gate • Capacitance is proportional to S • Voltage is proportional to S • Frequency is inverse proportional to S

  5. Scaling – Transmission Line W W

  6. Interconnect • Ways to reduce interconnect power consumption • Shorter wire length • More spacing • Clock gating

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