Proposal Outline

1. Proposal Outline • Focus on PS module development • Mechanical • Carbon foam, AlCF and thermal studies (UCD/FNAL) • CO2 thermal testing • Modeling • Interconnect and assembly • Full MPA mechanical bump bonded assembly • MaPSA initial PS test assembly • Assembly • Chip Testing • Z interconnect • TSV Studies (costs are substantial) • Other interconnect (wirebond, vertical circuits, interposer) • Tracklets – do we pursue this only in the context of Ted’s proposal? • Completion of Long barrel/3D studies • VICTR testing

2. Changes from LOI • Drop DC-DC converter studies • This is important for CMS but we do not have the critical mass for this work. It is being pursued in other venues and hopefully better solutions will be found • Drop active edge – pursue this as generic R&D • We continue to pursue this work, which could be quite important, as Fermilab generic R&D. • Focus on “baseline” design • The baseline design has either ALCF or carbon foam spacers and cooling pipes buried in a CF rod.

3. Future It is rather clear that our current level of contribution are less than we would like or are appropriate for the US investment we expect in the tracker project. CERN is doing much of the design work on the outer tracker. Here are some items for discussion. • Stronger involvement in sensors – what is the current proposal? • Does it make sense to develop a US vendor? (there is interest) • Stronger involvement in the chip design and testing • Alternate powering – we started serial powering work for ILC and developed a chip (SPI). It has now come back as a possibility due to the very high power density in the pixels • A stronger role in the module design and test • Involvement in the forward extension? • A natural area for US involvement • Large area active edge devices

4. Module with Edge Interconnects Correlation for tracks that cross Z boundries are difficult Where interconnects are at edge Long Strip tier ~mm Pixel tier All connections at Outer edge ~10 cm

5. Module with TSV Correlation for tracks that cross Z boundries are difficult Where interconnects are at edge Long Strip tier ~mm Pixel tier TSV All connections at Outer edge ~10 cm

6. Interposer Implementation Central region carries digital signals And z information between chips Interposerwith analogsignals Pixel tier Carbon Foam Flex interconnect Long Strip tier ~10 cm Long strip signals pass through flex Long strip are ½ module length