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Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches

Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches. Xiuyuan Bi (1) , Zhenyu Sun (1) , Hai Li (1) and Wenqing Wu (2) (1)University of Pittsburgh (2)Qualcomm Inc. Introduction. Spin-transfer torque random access memory (STT-RAM):

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Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches

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  1. Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches Xiuyuan Bi(1), Zhenyu Sun(1), Hai Li(1) and Wenqing Wu(2) (1)University of Pittsburgh (2)Qualcomm Inc.

  2. Introduction • Spin-transfer torque random access memory (STT-RAM): • Challenges: Write errors. • In this work: • Reduce write errors. • Improve write performance.

  3. Outline • STT-RAM Basics • Asymmetric Bit Error Rate • Probabilistic Design Techniques • WRAP and VOW • Hybrid STT-RAM Cache Hierarchy • CONCLUSION

  4. STT-RAM Basics – Cell • STT-RAM Cell: • Transistor and MTJ (Magnetic Tunnel Junction); • MTJ: • Free Layer and Ref. Layer; • Read: Direction → Resistance; • Write: Current → Direction. Write-0 Free Layer Parallel (RLow), 0 Barrier Reference Layer Anti-Parallel (RHigh), 1 Write-1

  5. STT-RAM Basics – Stochastic Switching • Switching (writing) time of MTJ: • Random; • Write errors: • Unsuccessful switching; • To reduce error: • Longer write time; • Larger write current. Switching time (ns) 10 20 30 40 50

  6. Outline • STT-RAM Basics • Asymmetric Bit Error Rate • Probabilistic Design Techniques • WRAP and VOW • Hybrid STT-RAM Cache Hierarchy • CONCLUSION

  7. Asymmetric Bit Error Rate MTJ • Write-1 vs. Write-0: • With same write time: • Write-1 has higher bit error rate (BER) Write-1 Harder Biasing Condition

  8. Asymmetric Bit Error Rate T Current BER • Temperature: • Process Variations: • Larger impact on Write-1.

  9. Asymmetric Bit Error Rate Sub-Block (64 bit) 64b 64b …… 64b • Sub-Block: • sub-BLock Error Rate (BLER): • Data pattern: • Strength of ECC:None < Hamming < BCH Block (64 Byte) N0→1 BLER

  10. Outline • STT-RAM Basics • Asymmetric Bit Error Rate • Probabilistic Design Techniques • WRAP and VOW • Hybrid STT-RAM Cache Hierarchy • CONCLUSION

  11. Probabilistic Design • How to reduce the write errors? • Conventional Design: • Extend write time (Globally); • Use ECC; • Cons: • High latency/energy. • Still high error rate. • Proposed probabilistic design: • WRAP and VOW • High performance, low energy, low write error rate. Error Conv. Design Proposed Design Latency/energy

  12. Probabilistic Design -- WRAP Write Read Done • Write-verify-Rewrite with Adaptive Period (WRAP): • Zero write error rate. • Total latency: Compare match Not Match

  13. Probabilistic Design -- WRAP Write Pulse(τ) BLER Niter • Optimal write pulse width τopt exists. • τopt affected by N0->1 : • Tracing N0->1 is costly. • Using Hamming Weight to estimate N0->1

  14. Probabilistic Design -- WRAP • τopt configuration: • Stored in look up table; • 0, 1, 2~8, 9~36, 37~64; • Temperature influence included; • Circuit Diagram:

  15. Probabilistic Design -- WRAP • Performance overhead: • Selecting τopt : • No overhead. • Verify operation: • Same location, only 1.47ns for each verify. • High performance.

  16. Probabilistic Design -- VOW • For WRAP: • Verify stops the writes. • Further improve performance: • Write & verify simultaneously. • Major Challenge: • Total 4 possible voltages. • Frequently pre-charge.

  17. Probabilistic Design -- VOW • Solution: • Only verify write-1s. • When Write-1s finishes: • BER0 extremely low. • Verify One only: • Write-1s finish: stop; • Low sense complexity; • One-time precharge.

  18. Probabilistic Design -- VOW • Asymmetric Sense Amplifier (ASA): • Track the 0->1 switch; • Pre-charged to a sub-stable state; • Once switched to 1, OUT goes high.

  19. Probabilistic Design -- Evaluation • Baselines: • Other baseline: RWRV. • Error Rate:

  20. Probabilistic Design -- Evaluation • Write Latency: • Write Energy:

  21. Probabilistic Design -- Evaluation • Evaluation summary (vs. Hamming): • WRAP: • Zero Write Error; 40% less latency. • VOW: • Reduce error by 1011; 52% less latency (vs. Hamming).

  22. Outline • STT-RAM Basics • Asymmetric Bit Error Rate • Probabilistic Design Techniques • WRAP and VOW • Hybrid STT-RAM Cache Hierarchy • CONCLUSION

  23. Hybrid Cache Hierarchy • Using VOW as higher level cache: • Higher performance; • May contains errors, use parity check; • WRAP as Lower level cache: • Provide golden copy.

  24. Hybrid Cache Hierarchy • Baselines: Base-B and Base-T: • Both use Hamming Code for write error protection; • Base-B : L2 write-back; • Base-T : L2 write-through. • Evaluation Results: • Reduce write error rates by 10-18; • Higher performance (6.8%), Lower energy cost (15%).

  25. Outline • STT-RAM Basics • Asymmetric Bit Error Rate • Probabilistic Design Techniques • WRAP and VOW • Hybrid STT-RAM Cache Hierarchy • CONCLUSION

  26. Conclusion • STT-RAM has random write errors; • Write-1 has higher error rate than write-0; • Two probabilistic design proposed to reduce write error while improve performance: • WRAP and VOW. • A hybrid cache hierarchy is proposed to reduce error rate while improve system performance.

  27. Thanks. Question?

  28. backup

  29. Hybrid Cache Hierarchy • Write failure probability (WFP): • Performance:

  30. Hybrid Cache Hierarchy • Energy: • Evaluation Results: • Reduce write error rates by 10-18; • Higher performance (6.8%) and Lower energy cost (15%).

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