Digital Systems Design

1. Digital Systems Design VHDL simulation of a 3 – Bit Binary Decoder with Enable by Marc A. Mackey

2. 3 - Bit Binary Decoder

3. List of eight address selections in hex • address select is in hex • 000 • 001 • 010 • 011 • 100 • 101 • 110 • 111

4. Output Description • E is the enable when the enable is low all outputs are zero • D0 is high when 000 is addressed and E is high • D1 is high when 001 is addressed and E is high • D2 is high when 010 is addressed and E is high • D3 is high when 011 is addressed and E is high • D4 is high when 100 is addressed and E is high • D5 is high when 101 is addressed and E is high • D6 is high when 110 is addressed and E is high • D7 is high when 111 is addressed and E is high

5. VHDL Code for Decoder • --VHDL Code For The 3-bit Decoder with Enable • library ieee; • use ieee.STD_LOGIC_1164.all; • entity decoder is • port ( • addr_sel : in std_ulogic; • E : in std_ulogic; • D0 : out std_ulogic; • D1 : out std_ulogic; • D2 : out std_ulogic; • D3 : out std_ulogic; • D4 : out std_ulogic; • D5 : out std_ulogic; • D6 : out std_ulogic; • D7 : out std_ulogic • ); • end decoder;

6. VHDL Code for Decoder (cont’d) • architecture decoder of binary is • begin • process (addr_sel , E) • begin • if (E = '1') then • case addr_sel(2 downto 0) is • when "000" =>D0 <= "00000001"; • when "001" =>D1 <= "00000010"; • when "010" =>D2 <= "00000100"; • when "011" =>D3 <= "00001000"; • when "100" =>D4 <= "00010000"; • when "101" =>D5 <= "00100000"; • when "110" =>D6 <= "01000000"; • when "111" =>D7 <= "10000000"; • end case; • end if; • end process; • end decoder;

7. VHDL Simulation

8. Vote of Thanks • James Freebourn–Harris Corp. • Melbourne, FL • jfreebou@harris.com