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Verilog HDL in Low Level Design

Verilog HDL in Low Level Design. From Logic gate level To Transistor level design. By Theerayod Wiangtong Electronic Department, Mahanakorn University of Technology. Outline. MOS revisit Static CMOS combinational circuit ASIC (Layout) design tools. MOS Structure. MOS Review.

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Verilog HDL in Low Level Design

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  1. Verilog HDL in Low Level Design From Logic gate level To Transistor level design By Theerayod Wiangtong Electronic Department, Mahanakorn University of Technology

  2. Outline • MOS revisit • Static CMOS combinational circuit • ASIC (Layout) design tools

  3. MOS Structure

  4. MOS Review • Transistor gate, source, drain all have capacitance • I = C (DV/Dt) -> Dt = (C/I) DV • Capacitance and current determine speed • MOS symbol

  5. MOS Capacitor • Gate and body form MOS capacitor • Operating modes • Accumulation • Depletion • Inversion

  6. Terminal Voltages • Mode of operation depends on Vg, Vd, Vs • Vgs = Vg – Vs • Vgd = Vg – Vd • Vds = Vd – Vs = Vgs - Vgd • Source and drain are symmetric diffusion terminals • By convention, source is terminal at lower voltage • Hence Vds 0 • nMOS body is grounded. First assume source is 0 too. • Three regions of operation • Cutoff • Linear • Saturation

  7. nMOS Cutoff • No channel • Ids = 0

  8. nMOS Linear • Channel forms • Current flows from d to s • e- from s to d • Ids increases with Vds • Similar to linear resistor

  9. nMOS Saturation • Channel pinches off • Ids independent of Vds • We say current saturates • Similar to current source

  10. nMOS I-V Summary • Shockley 1st order transistor models

  11. Example • We will be using a 0.6 mm process for your project • From AMI Semiconductor • tox = 100 Å • m = 350 cm2/V*s • Vt = 0.7 V • Plot Ids vs. Vds • Vgs = 0, 1, 2, 3, 4, 5 • Use W/L = 4/2 l

  12. pMOS I-V • All dopings and voltages are inverted for pMOS • Mobility mp is determined by holes • Typically 2-3x lower than that of electrons mn • 120 cm2/V*s in AMI 0.6 mm process • Thus pMOS must be wider to provide same current • In this class, assume mn / mp = 2

  13. Current-Voltage RelationsLong-Channel Device Second Order Effect

  14. -4 -4 x 10 x 10 2.5 6 VGS= 2.5 V VGS= 2.5 V 5 2 Resistive Saturation VGS= 2.0 V 4 VGS= 2.0 V 1.5 (A) (A) 3 D D VDS = VGS - VT I I VGS= 1.5 V 1 2 VGS= 1.5 V VGS= 1.0 V 0.5 1 VGS= 1.0 V 0 0 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 V (V) V (V) DS DS ID versus VDS Long Channel Short Channel 3: CMOS Transistor Theory

  15. V DD CMOS Inverter N Well PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND 4: DC and Transient Response

  16. Two Inverters Share power and ground Abut cells Connect in Metal 4: DC and Transient Response

  17. t = f(R .C ) pHL on L = 0.69 R C on L CMOS Inverter as Switch V V DD DD R p V out V out C L C L R n V 0 V V 5 5 in DD in (a) Low-to-high (b) High-to-low 4: DC and Transient Response

  18. DC Response • DC Response: Vout vs. Vin for a gate • Ex: Inverter • When Vin = 0 -> Vout = VDD • When Vin = VDD -> Vout = 0 • In between, Vout depends on transistor size and current • By KCL, must settle such that Idsn = |Idsp| • We could solve equations • But graphical solution gives more insight

  19. Transistor Operation • Current depends on region of transistor behavior • For what Vin and Vout are nMOS and pMOS in • Cutoff? • Linear? • Saturation?

  20. DC Transfer Curve • Transcribe points onto Vin vs. Vout plot

  21. Operating Regions • Revisit transistor operating regions

  22. Beta Ratio • If bp / bn 1, switching point will move from VDD/2 • Called skewed gate • Other gates: collapse into equivalent inverter

  23. Noise Margins • How much noise can a gate input see before it does not recognize the input?

  24. Logic Levels • To maximize noise margins, select logic levels at

  25. Logic Levels • To maximize noise margins, select logic levels at • unity gain point of DC transfer characteristic

  26. Delay Definitions • tpdr: rising propagation delay • From input to rising output crossing VDD/2 • tpdf: falling propagation delay • From input to falling output crossing VDD/2 • tpd: average propagation delay • tpd = (tpdr + tpdf)/2 • tr: rise time • From output crossing 0.2 VDD to 0.8 VDD • tf: fall time • From output crossing 0.8 VDD to 0.2 VDD • tcdr: rising contamination delay • From input to rising output crossing VDD/2 • tcdf: falling contamination delay • From input to falling output crossing VDD/2 • tcd: average contamination delay • tpd = (tcdr + tcdf)/2

  27. Delay Definitions

  28. Delay Definitions

  29. Delay Definitions

  30. Simulated Inverter Delay • Solving differential equations by hand is too hard • SPICE simulator solves the equations numerically • Uses more accurate I-V models too! • But simulations take time to write

  31. Outline • MOS revisit • Static CMOS combinational circuit • ASIC (Layout) design tools

  32. 1. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss 2. The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). 3. This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static CMOS Circuit

  33. Static Complementary CMOS VDD In1 PMOS only In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN PUN and PDN are dual logic networks

  34. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high

  35. PMOS Transistors in Series/Parallel Connection

  36. CL CL CL CL Threshold Drops VDD VDD PUN S D VDD D S 0  VDD 0  VDD - VTn VGS PDN VDD 0 VDD |VTp| VGS D S VDD S D

  37. Complementary CMOS Logic Style

  38. Example Gate: NAND

  39. Example Gate: NOR

  40. B A C D Complex CMOS Gate OUT = D + A • (B + C) A D B C

  41. V DD Standard Cells N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” 2 Out In Rails ~10 GND Cell boundary

  42. V DD Standard Cells 2-input NAND gate A B Out GND

  43. V V DD DD Stick Diagrams Contains no dimensions Represents relative positions of transistors Inverter NAND2 Out Out In A B GND GND

  44. A C B A B C VDD VDD X X GND GND uninterrupted diffusion strip Two Stick Layouts of !(C • (A + B))

  45. Connection label layout

  46. VDD, VSS and Output Labels

  47. Interconnected

  48. CMOS Properties • Full rail-to-rail swing; high noise margins • Logic levels not dependent upon the relative device sizes; ratioless • Always a path to Vdd or Gnd in steady state; low output impedance • Extremely high input resistance; nearly zero steady-state input current • No direct path steady state between power and ground; no static power dissipation • Propagation delay function of load capacitance and resistance of transistors

  49. Rp Rp Rp Rp Rp Rp A A A B B A Cint Rn CL CL CL Rn Rn Rn Rn B A B A A Cint Switch Delay Model Req A A NOR2 INV NAND2

  50. Rp Rp B A Cint CL Rn A Input Pattern Effects on Delay • Delay is dependent on the pattern of inputs • Low to high transition • both inputs go low • delay is 0.69 Rp/2 CL • one input goes low • delay is 0.69 Rp CL • High to low transition • both inputs go high • delay is 0.69 2Rn CL Rn B

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