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A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process

A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process. Chiou-Bang Chen , Horng-Yuan Shih Industrial Technology Research Institute. Outline. Introduction of frequency synthesizers Design objective M DLL topology and principle Measurement results Conclusions.

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A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process

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  1. A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process Chiou-Bang Chen, Horng-Yuan ShihIndustrial Technology Research Institute

  2. Outline • Introduction of frequency synthesizers • Design objective • MDLL topology and principle • Measurement results • Conclusions

  3. Introduction • PLL (phase-locked loop ) • Advantage : easy for frequency multiplication • Drawback : phase noise accumulation • DLL (delay locked loop ) • Advantage : no jitter accumulation • Drawback : frequency multiplication is difficult • MDLL (multiplying delay locked loop ) • Overcome the drawbacks of PLL and DLL

  4. Design Objectives

  5. Proposed MDLL - architecture Cc

  6. Proposed MDLL – time diagram 1 cycle M-1 cycles Mth cycle Mth cycle • The MDLL adventages: • Jitter accumulation will be reset every Mth cycle. • Programmable clock multiplication ratio • The phases of bclk (output) and rclk (input) are the same.

  7. Mux & Delay cell C 1/gm OUTN OUTP • Delay cell design : Duty cycle tuning circuit (Future work)

  8. Mux & Delay cell – duty cycle error Switch OUTN • Delay cell design issue • The switching action will generate duty cycle error.

  9. Delay control circuit Comparator Current mirror • The delay control circuit : • Vcont is reference voltage. • VDctl is the voltage on capacitor Cc. • After comparing, the arrangement of current determines oscillating frequency.

  10. The phase detector and charge pump • The design points : • Phase detector use the AND architecture. • The length of M1~M4 should be larger enough for channel length modulation.

  11. Selection signal generation circuit • The delay control circuit : • Using two DFF_divider and one NOR logic circuit generate LAST signal • Using dynamic phase detector generates SEL signal • A rare case of missing rclk edge

  12. Die Photograph • 90nm CMOS • 1x1 mm2

  13. Measurement Setup SIGNAL GENERATOR MDLL Analog Input 100MHz Digital Output & FFT Oscilloscope SIGNAL SOURCE ANALYZER

  14. Measured Output Spectrum

  15. Measured RMS jitter

  16. Measured transient Unlocked waveform Locked waveform

  17. Performance Summary

  18. Conclusions • The design points : • Switching action can reset the accumulation jitter, but it generates duty cycle error. • The phase detector uses AND logic to reduce the phase error pulse. • The length of MOS on charge pump should be large enough for channel length modulation. • In a rare case of a missing rclk edge, it makes the large phase error.

  19. Thanks for your attention

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