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A CMOS 5-GHz Micro-Power LNA. Hsieh-Hung Hsieh and Liang-Hung Lu. Department of Electrical Engineering and Graduate Institute of Electrics Engineering National Taiwan University, Taipei, Taiwan, ROC. 指導教授 : 林志明 教授 學生 : 黃世一. Outline. Abstract Introduction Circuit design and analysis
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A CMOS 5-GHz Micro-Power LNA Hsieh-Hung Hsieh and Liang-Hung Lu Department of Electrical Engineering and Graduate Institute of Electrics Engineering National Taiwan University, Taipei, Taiwan, ROC 指導教授 : 林志明 教授 學生 : 黃世一
Outline • Abstract • Introduction • Circuit design and analysis • Experimental results • Conclusion • References
Abstract • LNA for ultra-low-voltage and ultra-low-power application in standard 0.18μm CMOS technology • With complement current-reused gain stages • 9.2-dB gain and 4.5-dB noise figure at 5 GHz • 0.6 V supply voltage and 0.9mW power consumption
Introduction • CMOS for lower cost and higher level of integration • RF, inherently low transconductance • Typical CMOS, high bias current and high power consumption, battery lifetime ↓
The supply voltage for CMOS RF circuit • Feature size↓and supply voltage ↓ • When supply voltage below 1 V performance ↓
LNA of receiver is most power-consumption components • Current-reused LNA for NMOS • Folded cascode LNA • Novel current-reused topology for complementary cascade amplifier
Circuit design and analysis C1,LD1,C2,LD2 Inter-stage matching and dc block A. LNA Topology 1.VDD between Vth and 2Vth 2.VD=1/2 VDD Current-reused topology Input matching
The micrograph of the fabricated LNA 0.86*1.1mm2
Conclusion • A micro-power LNA using a standard 0.18μm CMOS technology • BY employing current-reused topology and inter-stage resonance technique • 9.2-dB power gain and 4.5-dB noise figure at 5 GHz • 0.9mw dc power consumption from an ultra-low supply voltage of 0.6 V
References • H.-H. Hsieh and L.-H. Lu, “A CMOS 5-GHz micro-power LNA,”IEEE RFIC Symposium, pp. 31-34, Jun. 2005