CMA LVL1 Barrel status

1. CMA LVL1 Barrel status • CM ASIC status • Splitter tests and status • PAD tests and status • ROD demonstrator status • Slice test preparation ATLAS Muon week 8th October 2003 S. Veneziano, INFN-Roma

2. Coincidence Matrix ASIC Functionality • The Coincidence Matrix ASIC performs most of the functions needed for the low-pT and high-pT triggers and for the read-out of the ATLAS Barrel Level1 Muon Trigger • Trigger and readout of 192 RPC FE signals • Timing and digital shaping of the signals coming from the RPC doublets • Execution of the trigger algorithm, local muon track candidates identification and pT classification • ROI overlap flagging • Data storage during Level1 latency • Storage of readout data in derandomizing memory • RPC hit time measurement with 3.125 LSB (1/8 BC) • Readout data serializer S. Veneziano, INFN-Roma

3. Timing Block • CMA has 3 clock domains, 2 working modes • Initialization mode: • all blocks are driven by the external 40 MHz clock • the PLL is bypassed and the 160 MHz clock divider is excluded • all registers are accessible as shift registers, driven by the I2C interface. • Run mode. • the PLL is in lock mode, provides the 320 MHz clock, and drives the 160 MHz clock generator. S. Veneziano, INFN-Roma

4. Input Pipeline Block • Front-end signal digital shaping is programmable in the range 1/8÷1 BC. • Pipeline delay is programmable in the range 3/8÷3 BCs • FE signal dead time is programmable in the range 0÷4 BCs, in steps of 1/8 BC S. Veneziano, INFN-Roma

5. Trigger Block • Coincidence logic works at 320 MHz • Number of matrices/thresholds is 3, logic is repeated three times in parallel, one per threshold setting • Majority logic is 1/4, 2/4 (one hit per doublet), 3/4, 4/4 • The highest threshold k-pattern which has a non-zero trigger information is shaped in time and then sent to the chip output pads S. Veneziano, INFN-Roma

6. RPC average cluster size is ~1.4. De-clustering logic type can be selected at CMA initialization. Max processed cluster size is programmable (up to ±3). Correlates hits from two detector layers 2/2 hits favoured over 1/2. programmable h<0, h=0, h>0 modes can be selected at CMA initialization. De-clustering + preprocessing S. Veneziano, INFN-Roma

7. Readout Block S. Veneziano, INFN-Roma

8. Readout block • The latency buffer stores hit patterns coming from the input FIFO until they get old • The input FIFO buffer is written at 320 MHz and contains the hit pattern, BCID and time interpolator value. The readout part of this buffer, together with the rest of the readout logic works at 160 MHz • In the derandomizer buffer, hits belonging to the same L1ID are assembled in data frame • All buffer memories are implemented with FIFOs • FIFO1 and FIFO2 contain a list of L1IDs and relative BCIDs respectively to be processed by the derandomizer and ready to be sent via the serializer • The serializer block attaches CRC codes to event fragments and ships the data out, following the DS-link protocol, at a programmable frequency of 10-80 MHz S. Veneziano, INFN-Roma

9. SEU detection • One parity bit is stored when register is initialized • Register parity is checked against stored parity every clock cycle • SEU output signal active when parity check fails • Single Event Upset detection has been implemented for almost all CMA registers • For the fundamental chip control registers (Main Control Register, Latency Registers, DSlink Register), triple redundancy, 2/3 majority, has been implemented for error correction. S. Veneziano, INFN-Roma

10. Testability • 32+5 serial scan chains, JTAG boundary scan, I2C register access • Scan chains (including RAM chains) used during ASIC acceptance tests: • All core registers and all RAMs are accessible via scan chains • Dedicated scan chains have been designed for RAM data, addresses and control signals, in order to be able to test the RAM cores • JTAG for tests during board assembly test • I2C is used for register accessibility and test pattern generation during trigger operation • Input pipelines can be preloaded with hit patterns and chip can be run for a fixed programmed number of cycles S. Veneziano, INFN-Roma

11. Design flow • VHDL RTL code • VHDL testbenches for all blocks and full chip • Design exploration synthesis • Top-down compile core and timing blocks • Scan chains, JTAG and IO pads insertion • Place & routing • Clock tree • Parasitic capacitance extraction • Final layout S. Veneziano, INFN-Roma

12. ASIC History • CMA ASIC submitted 20th November 2001 • 49 dies packaged by March 15th with four-pin bonding following preliminary specs (package 0208).New wafers had to selected for packaging with final Bonding. • Loadboard arrived 10th March to test site (Milano), following specifications (package 0219), had to be fixed to package 0208. • Industry tests started 21st March on 49 packages 0208 with scan tests. S. Veneziano, INFN-Roma

13. History 2 • 7th April functional tests sent by Rome to industry • 15th April 5 0208 tested devices (no RAM tests) and loadboard sent to Rome. • 20th April RAM test vectors sent by Rome to industry. • 29th April 44 fully tested 0208 package devices at Microtech. • 23rd May 37 devices with package 0219 tested at Microtech. S. Veneziano, INFN-Roma

14. CMA Layout • UMC 0.18 mm, 6 metal layers, 1.8 V core power supply, 3.3 V I/O pads • 430 kgates • Chip area: 4.5×4.5 mm2 • Virtual Silicon standard cell library • 320 MHz PLL (x8) macro • 24 double-port RAMs • 352 pins BGA package S. Veneziano, INFN-Roma

15. CMA ASIC pinout • Package 0208 and 0219 differ only on the position of PLL signals and supplies. Both of them are working correctly S. Veneziano, INFN-Roma

16. CMA Loadboard • Loadboard developped for Teradyne tester, has been designed with additional connectors for PLL test and lab tests in Rome. S. Veneziano, INFN-Roma

17. Test patterns • Scan and functional tests were performed on Teradyne machine at 1 Mhz, 40 Mhz, at room and at 125C temperatures. PLL lock was also tested. • SCAN tests: 32 scan chains, maximum of 900 cells, generated with Synopsys Test Compiler. • RAM tests: using single dedicated scan chain (23,743,440 cycles), generated from RTL model adn converted to compressed ATP format. • Functional tests 105576 vectors, to test I2C interface and start PLL, generated from full netlist+timing simulation, converted to ATP format. S. Veneziano, INFN-Roma

18. Industrial test results • 49 “0208” packages tested: • 7 failing on GND • 1 RAM fail • 1 SCAN fail • 40 OK (81.6% yield) • 37 “1219” packages tested: • No GND fails (already discarded?) • 4 RAM fails • 3 SCAN fails • 30 OK (81.1% yield) • 70 ASICs good, to be used for further tests and irradiation. S. Veneziano, INFN-Roma

19. LAB setup 36x64K T=6.125ns Pattern generator Clock jitter Waveform Analyser T=10ns GPIB LAN Generator PODs loadboard S. Veneziano, INFN-Roma I2C on RJ45

20. Tests done in Rome • LAB setup with limited capability has been used to do preliminary tests. • I2C on parallel port interface and C++ linux application has been used to initialize ASIC on all tests shown here. • Four CM ASICs mounted on CM boards will be used for further tests. S. Veneziano, INFN-Roma

21. PLL tests • 160 MHz derived clock output has been used to check PLL stability (320 MHz) 40 MHz input 160 MHz on dedicated IO S. Veneziano, INFN-Roma

22. PLL tests 2 • PLL has been characterized vs V and vs input Frequency. • PLL is working to specifications S. Veneziano, INFN-Roma

23. PLL vs Voltage S. Veneziano, INFN-Roma

24. PLL vs frequency S. Veneziano, INFN-Roma

25. Trigger test on a limited number of input channels, due to limitations on the laboratory setup Minimum pulse width measurement: Twmin > 6.126 ns (12 ns in specs) Dead timer, pulse shaping and pipeline delay working according to specs. Trigger output latency: Input to K-pattern delay Tlatkpat = (59 ± 1) ns Input to THR/OVL delay Tlatthr = (63÷88 ± 1) ns Skew between THR and OVL signals Toutskew = (2 ± 0.5) ns Trigger test S. Veneziano, INFN-Roma

26. Readout tests • Readout link is a two-wire Dslink protocol working at 80-40-20-10-5-2.5-1.125 Mbit/s • Readout tests done at 40 Mbit/s using: • 10ns period sampling with waveform analyser • GPIB LAN box connected to waveform analyser 8-bitCRC CMID L1ID … BCID + 16-bit hits … S. Veneziano, INFN-Roma

27. Readout tests 2 • VISA-GPIB library (linux) in deserializer program has been used to convert waveform vectors to readout data fragments. c151 -- CMID 0 FEL1ID 337 87d8 -- FEBCID 2008 0700 -- BC 0 TIME 7 IJK 0 STRIP 0 0745 -- BC 0 TIME 7 IJK 2 STRIP 5 0685 -- BC 0 TIME 6 IJK 4 STRIP 5 07c0 -- BC 0 TIME 7 IJK 6 STRIP 0 07e3 -- BC 0 TIME 7 OVL 0 THR 3 4075 -- CRC 75 S. Veneziano, INFN-Roma

28. Time interpolator linearity • Hits on four channels have been generated, in 1 ns steps, within a range of 4 BCs (CH 1-4), also trigger output time is measured (K). Very preliminary S. Veneziano, INFN-Roma

29. Readout bandwidth • Max LVL1 input frequency. 1% RPC occupancy 1-BC window S. Veneziano, INFN-Roma

30. Power vs voltage S. Veneziano, INFN-Roma

31. Power vs frequency Nominal power consumption during normal run mode operation is ~1.2 W S. Veneziano, INFN-Roma

32. CM board Eta RJ45 (from splitters) • PCBs to be mounted on PAD prototype are ready LVDS receivers CMA PAD Motherboard connections S. Veneziano, INFN-Roma

33. CM board Phi RN connectors (from wired-OR) • Four ASICs mounted on two eta and two phi boards on June. FE receivers CMA S. Veneziano, INFN-Roma

34. PAD Box CMA phi Optical link tx TTCrx ELMB PAD logic CMA eta Programmable Delay ASICs S. Veneziano, INFN-Roma

35. PAD status • Initialization of all Ics via CANbus has been tested: • PC (C++, IXXAT libraries) • ELMB custom firmware • FPGA JTAG flash, external 4 Mbit SPI flash, FPGA download tested with “dummy ELMB” (piggy w FPGA connected to parallel port) tested. • Now working on PAD readout logic, data collection from 1( then 8) CM ASICs and slow readout via I2C-CANbus. • VME ROD emulator, mounting new GLINK receiver piggy is almost ready S. Veneziano, INFN-Roma

36. Splitter status • Splitter prototypes have been used extensively in Naples and X5 test beam. • 320 channels available in X5 for ageing tests • New mechanical version being prepared (50% smaller) • Splitter Phi master and slave ready • Eta board and motherboard under revision • Aim at preproduction starting in December to equip: • Frascati integration test stand • H8 test beam • September 2003 S. Veneziano, INFN-Roma

37. SL/RX ROD emulator status • Receiver board: • One RX piggy, two 16 bit x 40 MHz channels • Two FIFOs accessible by VME • Four RX in final system: • Sector logic • RX board (1/2 ROD system) • PCB ready, last checks before sending for fabrication S. Veneziano, INFN-Roma

38. RPC slice preparation Splitter eta board Full specs Splitter Motherboard and phi boards full specs PAD OR board Full specs PAD motherboard full specs CM board eta full specs G-Link 32-bit RX-TX full specs, final CM board Phi full specs SL/ROD emulator S. Veneziano, INFN-Roma

39. Plans & Conclusions • CM ASIC 1st prototype is OK • Radiation Test and Slice test in H8 to understand if we need 2nd iteration. • Slice Test: • all on-detector slice components are now available • Off-detector emulator board almost ready • DAQ-1 is being installed in Rome slice test stand • Initialization software done with standalone program: • Test Beam in 2003 with RPC detector is THE milestone, before staring full production • Splitter production has to be launched as soon as we have final prototypes tested and final costing. PRR foreseen in December. S. Veneziano, INFN-Roma