Resolving interrupt conflicts

1. Resolving interrupt conflicts An introduction to reprogramming of the 8259A Interrupt Controllers

2. Intel’s “reserved” interrupts • Intel had reserved interrupt-numbers 0-31 for the processor’s various exceptions • But only interrupts 0-4 were used by 8086 • Designers of the early IBM-PC ROM-BIOS disregarded the “Intel reserved” warning • So interrupts 5-31 got used by ROM-BIOS code for its own various purposes • This created interrupt-conflicts for 80286+

3. Exceptions in Protected-Mode • The interrupt-conflicts seldom arise while the processor is executing in Real-Mode • PC BIOS uses interrupts 8-15 for devices (such as timer, keyboard, printers, serial communication ports, and diskette drives) • CPU uses this range of interrupt-numbers for various processor exceptions (such as page-faults, stack-faults, protection-faults)

4. Handling these conflicts • There are two ways we can ‘resolve’ these interrupt-conflicts when we write ‘handlers’ for device-interrupts in the ‘overlap’ range • We can design each ISR to query the system in some way, to determine the ‘cause’ for the interrupt-condition (i.e., a device or the CPU?) • We can ‘reprogram’ the Interrupt Controllers to use non-conflicting interrupt-numbers when the peripheral devices trigger their interrupts

5. Learning to program the 8259A • Either solution will require us to study how the system’s two Programmable Interrupt Controllers are programmed • Of the two potential solutions, it is evident that greater system efficiency will result if we avoid complicating our interrupt service routines with any “extra overhead” (i.e., to see which component wished to interrupt)

6. Three internal registers input-signals 8259A IRR output-signal IMR ISR IRR = Interrupt Request Register IMR = Interrupt Mask Register ISR = In-Service Register

7. PC System Design 8259A PIC (master) CPU 8259A PIC (slave) INTR Programming is via I/O-ports 0x20-0x21 Programming is via I/O-ports 0xA0-0xA1

8. How to program the 8259A • The 8259A has two modes: • Initialization Mode • Operational Mode • Operational Mode Programming: • Write a (9-bit) command to the PIC • Maybe read a return-byte from the PIC • Initialization Mode Programming: • Write a complete initialization sequence

9. How to access the IMR • If in operational mode, the Interrupt Mask Register (IMR) can be read or written at any time (by doing in/out with A0-line=1) • Read the master IMR: in $0x21, %al • Write the master IMR: out %al, $0x21 • Read the slave IMR: in $0xA1, %al • Write the slave IMR: out %al, $0xA1

10. How to read the master IRR • Issue the “read register” command-byte, with RR=1 and RIS=0; read return-byte: mov $0x0B, %al out %al, $0x20 in $0x20, %al

11. How to read the master ISR • Issue the “read register” command-byte, with RR=1 and RIS=1; read return-byte: mov $0x0A, %al out %al, $0x20 in $0x20, %al

12. End-of-Interrupt • In operational mode (unless AEOI was programmed), the interrupt service routine must issue an EOI-command to the PIC • This ‘clears’ an appropriate bit in the ISR and allows other unmasked interrupts of equal or lower priority to be issued • The non-specific EOI-command clears the In-Service Register’s highest-priority bit

13. Some EOI examples • Send non-specific EOI to the master PIC: mov $0x20, %al out %al, $0x20 • Send non-specific EOI to both the PICs: mov $0x20, %al out $%al, 0xA0 out %al, $0x20

14. Initializing the 8259A • A series of 9-bit values is sent to the PIC • Once it’s begun, it must be completed • Each 9-bit values is called an Initialization Command Word (abbreviated ICW) • The least significant 8 bits are sent on the PC’s data-bus, while the 9th bit is sent as bit 0 on the PC’s address-bus

15. Official Reference • The official Intel programming reference manual for the 8259A is available online (see ‘Resources’ on our course website) • This document is 24 pages in .pdf format • Many pages are irrelevant to programmers (e.g., they are concerned with electrical specifications, physical dimensions, pin configurations, and heating restrictions)

16. ICW1 and ICW2 0 A7 A6 A5 1 LTIM ADI SNGL IC4 ICW1 1 A15 / T7 A14 / T6 A13 / T5 A12 / T4 A11 / T3 A10 A9 A8 ICW2 LTIM (1 = Level-Triggered Interrupt Mode, 0 = Edge-Triggered Interupt Mode) ADI is length of Address-Interval for call-instruction (1 = 4-bytes, 0 = 8-bytes) SNGL (1 = single controller system, 0 = multiple controllers in cascade mode) IC4 means Initialization Command-Word 4 is needed (1 = yes, 0 = no)

17. ICW3 1 S7 S6 S5 S4 S3 S2 S1 S0 (master) S Interrupt-Request Input is from a slave controller (1=yes, 0=no) 1 0 0 0 0 0 ID2 ID1 ID0 (slave) ID number of slave controller’s input-pin to master controller (0-7)

18. ICW4 1 0 0 0 SFNM BUF M / S AEOI µPM microprocessor mode 1=8086/8088 0=8080 Special Fully-Nested Mode (1 = yes, 0 = no) NON-BUFFERED mode (00 or 01) BUFFERED-MODE (10 = slave, 11 = master) Automatic EOI mode 1 = yes, 0 = no

19. Initializing the master PIC • Write a sequence of four command-bytes • (Each command is comprised of 9-bits) A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 1 ICW1=0x11 1 ICW2=baseID 1 0 0 0 0 0 1 0 0 ICW3=0x04 1 0 0 0 0 0 0 0 1 ICW4=0x01

20. Initializing the slave PIC • Write a sequence of four command-bytes • (Each command is comprised of 9-bits) A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 1 ICW1=0x11 1 ICW2=baseID 1 0 0 0 0 0 0 1 0 ICW3=0x02 1 0 0 0 0 0 0 0 1 ICW4=0x01

21. Unused real-mode ID-range • We can use our ‘showivt.s’ demo to see the “unused” real-mode interrupt-vectors • One range of sixteen consecutive unused interrupt-vectors is 0x90-0x9F • We created a demo-program (‘reporter.s’) to ‘reprogram’ the 8259s to use this range • This could be done in protected-mode, too • It would resolve the interrupt-conflict issue

22. Other ideas in the demo • It uses an assembly language ‘macro’ to create sixteen different ISR entry-points: .macro isr id pushf pushw $\id call action .endm • All the instances of this macro call to a common interrupt-handling procedure (named ‘action’)

23. The Macro’s expansion • If the macro-definition is invoked, with an argument equal to, say, 0x08, like this: isr 0x08 then the ‘as’ assembler will ‘expand’ that macro-invocation, replacing it with: pushf pushw $0x08 call action

24. How ‘action’ works • Upon entering the ‘action’ procedure, the system stack has six words: • The two “topmost” words (at bottom of picture) will get replaced by the interrupt-vector corresponding to ‘int-ID’ FLAGS CS IP FLAGS Interrupt-ID return-from-action SS:SP

25. The stack states Stage 1 Stage 2 Stage 3 Stage 4 FLAGS FLAGS FLAGS FLAGS CS CS CS CS IP IP IP IP FLAGS FLAGS Upon entering ‘isr’ After exiting ‘action’ (and entering ROM-BIOS interrupt- handler) Int-ID vector-HI action-return vector-LO Upon entering ‘action’ Before exiting ‘action’

26. The on-screen status-line • We call ROM-BIOS services to setup the video display-mode for 28-rows of text • We use lines 0 through 24 for the standard 80-column by 25-rows of text output • Line 25 is kept blank (as visual separator) • Lines 26 and 27 are used to show sixteen labeled interrupt-counters (IRQ0-IRQ15) • Any device-interrupt increments a counter

27. In-class exercise • The main new idea was reprogramming of the 8259A Interrupt Controllers, in order to avoid “overloading” of any Intel “reserved” interrupt-numbers: 0x00 - 0x1F • Modify our ‘tickdemo.s’ program so that a timer-tick interrupt in protected-mode will get routed through Interrupt Gate 0x20 (instead of through “reserved” Gate 0x08)