CMPUT229 - Fall 2003

CMPUT229 - Fall 2003 Topic9: Handling Exceptions José Nelson Amaral CMPUT 229 - Computer Organization and Architecture I

Reading Material The slides for this topic are based on the Chapter 12 of the following book: Goodman, James and Miller Karen, A Programmer’s View of Computer Architecture with Assembly Language Examples from the MIPS RISC Architecure, Oxford University Press, 1993. CMPUT 229 - Computer Organization and Architecture I

Polling and Interruption Polling: Has to stop working every once in a while to see if there is someone in need of attention. Advantage: Never interrupted in the middle of a task, thus can plan when to stop to check. Disadvantages: 1. Will stop working several times to check when there is nobody there. 2. Someone might have to wait for a while until the next pooling opportunity to be noticed. CMPUT 229 - Computer Organization and Architecture I

Polling and Interruption Interruption: When someone needs attention that person will interrupt the work. Advantage: Never need to stop working if nobody needs attention. Disadvantages: 1. Will be stopped in the middle of a task. More difficult to save/restore state (context switching can be expensive). 2. Hardware and software must be involved to provide a context switching mechanism. CMPUT 229 - Computer Organization and Architecture I

Interruptions and Exceptions In the common use of the words (but not always and not by everyone): Interruption refers to a request for attention by a device that is external to the processor. For example the mouse driver or the keyboard driver will interrupt the processor to report a keystroke or a mouse click. Exception refers to a transfer of control caused by an internal condition in the processor. For instance if a program executing at the user level accesses an address at the kernel region, an illegal address access exception will be generated. CMPUT 229 - Computer Organization and Architecture I

The MIPS Exception Mechanism A MIPS processor operates in one of two modes: kernel and user. When running in the kernel mode, a program has access to an additional set of registers that are not accessible to a program running in the user mode. Memory locations in the upper half of the address space, i.e. memory locations whose most significant bit is 1, can only be accessed in the kernel mode. This region include: - Exception handler code - Data that is only accessible by the operating system - Memory-mapped I/O addresses CMPUT 229 - Computer Organization and Architecture I

Exception Program Counter Co-processor C0 Co-processor C0 only can be accessed when executing in the kernel mode. The registers of coprocessor C0 are accessed, when executing in the kernel mode, through the instructions mtc0 and mfc0 CMPUT 229 - Computer Organization and Architecture I

CP0 Registers Register NameReg. Number Context 4 BadVAddr (Bad Virtual Address) 8 Count 9 Compare register 11 Status 12 Cause 13 EPC (Exception Program Counter) 14 WatchLo (Mem. Ref. Trap Addr. Low) 18 WatchHi (Mem. Ref. Trap Addr. High) 19 Xcontext 20 ECC 26 CacheErr (Cache Error Status) 27 ErrorEPC (Erroe Except. Prog. Counter) 30 CMPUT 229 - Computer Organization and Architecture I

31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD 0 CE 0•••0 IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0 The Cause Register CMPUT 229 - Computer Organization and Architecture I

31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD 0 CE 0•••0 IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0 The Cause Register Exception Mnemonic Meaning Code 0 Int Interruption 1-3 TLB exceptions 4 AdEL Address error exception (load) 5 AdES Address error exception (store) 6 IBE Bus error on instruction fetch 7 DBE Bus error on data reference 8 Sys Syscall instruction 9 Break Break instruction 10 RI Reserved 11 CpU Co-processor unusable 12 Ov Arithmetic overflow 13 Tr Trap Exception 15 FPE Floating Point Exception 16-31 (future use) CMPUT 229 - Computer Organization and Architecture I

31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD 0 CE 0•••0 IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0 The Cause Register External Interrupts Software Interrupts CMPUT 229 - Computer Organization and Architecture I

27 26 31-28 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0 RP FR CU RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc External Interrupts Software Interrupts The Status Register CMPUT 229 - Computer Organization and Architecture I

27 26 31-28 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0 RP FR CU RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc External Interrupts Software Interrupts The Status Register KUc: Is the program running in kernel mode or user mode? PUp: Was the processor in kernel or user mode when the last exception occurred? IM(0)-IM(7): Interrupt Mask. It controls which interrupts are enabled. RE: Reverse-Endian (RE) bit. Reverses the endianess of the machine. FR: Enables additional floating point registers CU: 4 bits to control co-processor usability CMPUT 229 - Computer Organization and Architecture I

27 26 31-28 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0 RP FR CU RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc External Interrupts Software Interrupts The Status Register KUc: Is the program running in kernel mode or user mode? PUp: Was the processor in kernel or user mode when the last exception occurred? IM(0)-IM(7): Interrupt Mask. It controls which interrupts are enabled. RE: Reverse-Endian (RE) bit. Reverses the endianess of the machine. FR: Enables additional floating point registers RP: Enables reduced-power operation (reduce clock freq.) CU: 4 bits to control co-processor usability CMPUT 229 - Computer Organization and Architecture I

The (EPC) is a register of the co-processor C0. The content of the EPC can be transferred to a general register using the instruction: mfc0 $ri, $14 Invocation and Return from the Exception Handler The MIPS architecture fix a single address --- 0x8000 0080 --- to be the starting address of the exception handler. When an exception is invoked, control is transferred to this location. The exception invocation must also save the returning address for the exception. But it cannot save this address in $ra, because $ra contains the returning address for the routine that is currently executing. The Exception Program Counter (EPC) is loaded with the address at which processing resumes after an exception is serviced. CMPUT 229 - Computer Organization and Architecture I

Load Cause Register ExecCode? HandleInterrupt HandleSyscall HandleOverflow Restore registers Load EPC into $k0 Clean Up State Return Exception Handling Save registers CMPUT 229 - Computer Organization and Architecture I

31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD 0 CE 0•••0 IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0 AND Examining the Exception Code Exception Handler: <preliminary check for reentrance> OK: <set flag> <save registers> mfc0 $k0, $13 # Get the Cause Register andi $k0, $k0, $0x7c # Mask out the ExcCode bits lw $k0, JumpTable($k0) # Read address from jump table jr $k0 # Jump to exception handler $k0 = bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb 0x7c = 0000 0000 0000 0000 0000 0000 0111 1100 $k0 = 0000 0000 0000 0000 0000 0000 0bbb bb00 CMPUT 229 - Computer Organization and Architecture I

Examining the Exception Code Exception Handler: <preliminary check for reentrance> OK: <set flag> <save registers> mfc0 $k0, $13 # Get the Cause Register andi $k0, $k0, $0x7c # Mask out the ExcCode bits lw $k0, JumpTable($k0) # Read address from jump table jr $k0 # Jump to exception handler Return: <restore registers> <clear flag> mfc0 $k0, $14 # Get EPC register rfe # clean up state register jr $k0 # return to the address in EPC PS: In the MIPS R4000 the return from exception (rfe) instruction is called exception return (eret). Check the manual of the MIPS processor (or simulator) that you are using to find the correct instruction to return from an exception. CMPUT 229 - Computer Organization and Architecture I

31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD 0 CE 0•••0 IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0 Building the Jump Table (The Cause Register) Exception Mnemonic Meaning Code 0 Int Interruption 1-3 TLB exceptions 4 AdEL Address error exception (load) 5 AdES Address error exception (store) 6 IBE Bus error on instruction fetch 7 DBE Bus error on data reference 8 Sys Syscall instruction 9 Break Break instruction 10 CpU Co-processor unusable 12 Ov Arithmetic overflow 13 Tr Trap Exception 15 FPE Floating Point Exception 16-31 (future use) CMPUT 229 - Computer Organization and Architecture I

Building the Jump Table Exception Handler: JumpTable: .word HandleInt # Interrupt .word HandleMOD # TLB modification exception .word HandleTLBL # TLB miss exception (load or fetch) .word HandleTLBS # TLB miss exception (store) .word HandleAdEL # Address error exception (load or fetch) .word HandleAdES # Address error exception (store) .word HandleIBE # Bus error exception (for a fetch) .word HandleDBE # Bus error exception (for a load or store) .word HandleSys # Syscall exception .word HandleBp # Breakpoint exception .word HandleRI # Reserved Instruction Exception .word HandleCpU # Co-processor Unusable exception .word HandleOvf # Arithmetic overflow exception .word HandleFPInexact # Inexact floating point result .word HandleDivideBy0 # Divide by 0 .word HandleFPOvf # FP Overflow .word HandleFPUnder # FP Underflow .word HandleRes, HandleRes, HandleRes, HandleRes .word HandleRes, HandleRes, HandleRes, HandleRes .word HandleRes, HandleRes, HandleRes, HandleRes .word HandleRes, HandleRes, HandleRes, HandleRes CMPUT 229 - Computer Organization and Architecture I

The Syscall Handle In this example of exception handling, lets assume that we want to handle the following syscall functions: putc, puts, exit, and getc. In order to obtain one of this services, the user’s program must pass the following codes in $v0: $v0syscall service 12 getc 11 putc 10 exit 4 puts We assume that the value of $v0 was saved at the beginning of the exception service in the memory location tmpv0 CMPUT 229 - Computer Organization and Architecture I

The Syscall Handle Exception Handler: HandleSys: mfc0 $k1, $14 # Get the EPC Register addi $k1, $k1, 4 # Increment PC past syscall instruction mtc0 $k1, $14 # Set the EPC Register lw $v0, tmpv0 # get the previously saved value of $v0 li $a0, 11 # Is it putc? beq $v0, $a0, Putc li $a0, 4 # Is it puts? beq $v0, $a0, Puts li $a0, 12 # Is it getc? beq $v0, $a0, Getc li $a0, 10 # Is it exit? beq $v0, $a0, Exit la $a0, SysMessage # Bad number in $v0 jal Print String # Print message j Return CMPUT 229 - Computer Organization and Architecture I

The Syscall Handle Exception Handler: Exit: <code for Exit> Putc: <code for Putc> Puts: <code for Putc> Getc: <code for Getc> CMPUT 229 - Computer Organization and Architecture I

Checking for Reentrance Exception Handler: flag: .word 0 # remembers if it was already in the # exception handler when the exception # occurred BadReentry: .asciiz “Bad re-entry into kernel\nHalting\n” .ktext .space 0x80 # skip space so that the handler is at 0x80000080 add $k1, $at, $zero # immediately save $at lw $k0, flag # SPIM translates this instruction to: # lui $at, 4097 # lw $k0, 0($at) beq $k0, $zero, OK la $a0, BadReentry j Panic OK: <set flag> <save registers> mfc0 $k0, $13 # Get the Cause Register andi $k0, $k0, 0x7c # Mask out the ExcCode bits lw $k0, JumpTable($k0) # Read address from jump table jr $k0 # Jump to exception handler CMPUT 229 - Computer Organization and Architecture I

Code for Panic The code for Panic has to print the following message: Panic: Bad re-entry into kernel\nHalting\n CMPUT 229 - Computer Organization and Architecture I

Panic Exception Handler: DisplayData = 0xbfff0008 DisplayStatus = 0xbfff000c .kdata Pmess: .asciiz “Panic: “ .ktext # Panic prints a message and quits Panic: la $a1, Pmess PRead1: lb $a2, ($a1) # read letter to print beq $a2, $zero, PRead2 # done when we find a null PWait1: lw $a3, DisplayStatus # Read the status of the display bge $a3,$zero, PWait1 # keep reading until it is ready sw $a2, DisplayData # output character addi $a1, $a1, 1 # advance character j PRead1 PRead2: lb $a2, ($a0) # Print message pointed by $a0 beq $a2, $zero, Pcontinue # done when we find a null PWait2: lw $a3, DisplayStatus # Read the status of the display bge $a3, $zero, PWait2 # keep reading until it is ready sw $a2, DisplayData # output character addi $a0, $a0, 1 # advance character j PRead2 Pcontinue: li $v0, 0 # clear re-entrance flag sw $v0, flag li $v0, 13 # the quit_now syscall syscall CMPUT 229 - Computer Organization and Architecture I

Save/Restore Registers Exception Handler: <preliminary check for reentrance> OK: <set flag> <save registers> mfc0 $k0, $13 # Get the Cause Register andi $k0, $k0, $0x7c # Mask out the ExcCode bits lw $k0, JumpTable($k0) # Read address from jump table jr $k0 # Jump to exception handler Return: <restore registers> <clear flag> mfc0 $k0, $14 # Get EPC register rfe # clean up state register jr $k0 # return to the address in EPC .kdata tmpat: .word 0 tmpv0: .word 0 tmpa0: .word 0 tmpa1: .word 0 tmpa2: .word 0 tmpa3: .word 0 tmpra: .word 0 CMPUT 229 - Computer Organization and Architecture I

Save/Restore Registers .kdata tmpat: .word 0 tmpv0: .word 0 tmpa0: .word 0 tmpa1: .word 0 tmpa2: .word 0 tmpa3: .word 0 tmpra: .word 0 # code to save registers sw $k1, tmpat sw $v0, tmpv0 sw $a0, tmpa0 sw $a1, tmpa1 sw $a2, tmpa2 sw $a3, tmpa3 sw $ra, tmpra # code to restore registers lw $v0, tmpv0 lw $a0, tmpa0 lw $a1, tmpa1 lw $a2, tmpa2 lw $a3, tmpa3 lw $ra, tmpra sw $zero, flag # clear re-entry flag lw $k1, tmpat # restore $at add $at, $k1, $zero mfc0 $k0, $14 # Get EPC register rfe # clean up state register jr $k0 # return to the address in EPC CMPUT 229 - Computer Organization and Architecture I

Code for Putc Exception Handler: .kdata tmpputra: .word 0 .ktext Putc: lw $a0, tmpa0 jal Puta0 j Return Puta0: lw $k0, pqhead # load head of put queue lw $k1, pqtail # load tail of put queue addi $k1, 1 # increment tail andi $k1, $k1, 0x00ff # module counter beq $k1, $k0, Full # try to print a charn if queue is full sb $a0, putqueue($k1) # add byte to the queue sw $k1, pqtail # save new tail mfc0 $k1, $12 # Get status register ori $k1, 0x5000 # Turn on display interrupts mtc0 $k1, $12 # Set status register sw $ra, tmpputra # Save return address jal DP_handler # try to print lw $ra, tmpputra # Restore return address jr $ra Full: sw $ra, tmpputra # Save return address jal DP_handler # Try to print lw $ra, tmpputra # Restore return address j Puta0 CMPUT 229 - Computer Organization and Architecture I

Code for DP_handler Exception Handler: .kdata putqueue: .space 256 .align 2 .ktext pqtail: .word 0 pqhead: .word 0 .ktext DP_handler: lw $k0, DisplayStatus # Get display status word bge $k0, $zero, DPRet # Return if it is not Ready lw $k0, pqhead # lw $k1, pqtail beq $k0, $k1, DPRet # Return if put queue is empty addi $k0, $k0, 1 # Increment head andi $k0, $k0, 0x00ff # Module counter sw $k0, pqhead # Save new head lb $k0, putqueue($k0) # get character from put queue sb $k0, DisplayData # Send character to display DPRet: jr $ra # Return to caller CMPUT 229 - Computer Organization and Architecture I

Code for Puts Exception Handler: .kdata tmpputsra: .word 0 Puts: lw $k0, tmpa0 # Get address of first character PutsLoop: lbu $a0, ($k0) # Get a character beq $a0, $zero, PutsRet # If character is null, we are done sw $ra, tmpputsra # Save return address jal Puta0 # Print the character sw $ra, tmpputsra # Save return address addi $k0, $k0, 1 # Move pointer to next character j PutsLoop # Loop back PutsRet: jr $ra CMPUT 229 - Computer Organization and Architecture I

Bad Virtual Address Register The register $8 of the coprocessor 0 is the BadVAddr (Bad Virtual Address) register. It is a read only address register that contains the most recent virtual address that caused one of the following exceptions: TLB Invalid TLB Modified TLB Refill Virtual Coherency Data Access Virtual Coherency Instruction Fetch The BadVAddr does not save any information for bus errors, since bus errors are not addressing errors. CMPUT 229 - Computer Organization and Architecture I

CMPUT229 - Fall 2003