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CMPUT329 - Fall 2003

CMPUT329 - Fall 2003. Topic 8: Documentation and Timing Diagrams José Nelson Amaral. Reading . Sections 5.1, 5.2, 5.3, 5.4, 5.5 (Wakerly Textbook). In this topic we will cover: - Documentation styles - Timing Diagrams - Multiplexers - Decoders - PLAs. Documentation Standards.

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CMPUT329 - Fall 2003

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  1. CMPUT329 - Fall 2003 Topic 8: Documentation and Timing Diagrams José Nelson Amaral CMPUT 329 - Computer Organization and Architecture II

  2. Reading Sections 5.1, 5.2, 5.3, 5.4, 5.5 (Wakerly Textbook) In this topic we will cover: - Documentation styles - Timing Diagrams - Multiplexers - Decoders - PLAs CMPUT 329 - Computer Organization and Architecture II

  3. Documentation Standards • Block diagrams • first step in hierarchical design • Schematic diagrams • HDL programs (ABEL, Verilog, VHDL) • Timing diagrams • Circuit descriptions CMPUT 329 - Computer Organization and Architecture II

  4. Block Diagram CMPUT 329 - Computer Organization and Architecture II

  5. Schematic diagrams • Details of component inputs, outputs, and interconnections • Reference designators • Pin numbers • Title blocks • Names for all signals • Page-to-page connectors CMPUT 329 - Computer Organization and Architecture II

  6. Example schematic CMPUT 329 - Computer Organization and Architecture II

  7. Flat Schematic Structure CMPUT 329 - Computer Organization and Architecture II

  8. Hierarchical Schematic Structure CMPUT 329 - Computer Organization and Architecture II

  9. Other Documentation • Timing diagrams • Output from simulator • Specialized timing-diagram drawing tools • Circuit descriptions • Text (word processing) • Can be as big as a book (e.g., typical Cisco ASIC descriptions) • Typically incorporate other elements (block diagrams, timing diagrams, etc.) CMPUT 329 - Computer Organization and Architecture II

  10. Gate symbols CMPUT 329 - Computer Organization and Architecture II

  11. DeMorgan Equivalent Symbols Which symbol to use? Answer depends on signal names and active levels. CMPUT 329 - Computer Organization and Architecture II

  12. A B C=A·B C_L=A_L+B_L A_L B_L Viewing Gates in Positive or Negative Logic AND C=1 if and only if A=1AND B=1 C=0 if and only if A=0OR B=0 CMPUT 329 - Computer Organization and Architecture II

  13. A_L B_L C_L=A_L·B_L A B C=A+B Viewing Gates in Positive or Negative Logic OR C=1 if and only if A=1OR B=1 C=0 if and only if A=0AND B=0 CMPUT 329 - Computer Organization and Architecture II

  14. AND If A=1 AND B=1 then C=1 otherwise C=0 A B C=A·B A B C=A+B Logic Functions: Boolean Algebra INVERTER If X=0 then X’=1 If X=1 then X’=0 X X’ OR If A=1 OR B=1 then C=1 otherwise C=0 CMPUT 329 - Computer Organization and Architecture II

  15. Signal Names and Active Levels • Signal names are chosen to be descriptive. • Active levels -- HIGH or LOW • named condition or action occurs in either the HIGH or the LOW state, according to the active-level designation in the name. CMPUT 329 - Computer Organization and Architecture II

  16. Examples of Buses CMPUT 329 - Computer Organization and Architecture II

  17. Timing Diagrams CMPUT 329 - Computer Organization and Architecture II

  18. Timing Diagrams CMPUT 329 - Computer Organization and Architecture II

  19. Bus Timing Diagram CMPUT 329 - Computer Organization and Architecture II

  20. Bus Timing Diagram CMPUT 329 - Computer Organization and Architecture II

  21. A’ B’ I0 I0 4-to-1 MUX I1 Z I2 I3 Z A B’ I2 A B A B I3 A’ B I1 Multiplexers CMPUT 329 - Computer Organization and Architecture II

  22. A typical use of a MUX in a processor control path Consider the following sequence of instructions: 0x7F800 add $16, $18, $15 # reg16  reg18 + reg15 0x7F804 beq $8, $0, target # if reg16 == 0 goto target 0x7F808 sub $17, $17 $15 # reg17  reg17 - reg15 PC Mux Add 0 4 1 Branch Target Unit Branch taken CMPUT 329 - Computer Organization and Architecture II

  23. 1 I0 0 F(R,S,T) I1 T I2 T F(R,S,T) = R’S’•1 + RT•(S+S’) I3 = R’S’•1 + R’S•0 + RS•T + RS’•T R S 00 01 11 10 A 4-to-1 MUX can implem. any 3-variable function Example: Implement the function F(R, S, T) = R’S’ + RT Z A B Functions of how many input variables can be implemented by an 8-t0-1 MUX? Use an 8-t0-1 MUX to implement the function: F(X,Y,Z,T) = XY’ + Z’T CMPUT 329 - Computer Organization and Architecture II

  24. Decoders • General decoder structure • Typically n inputs, 2n outputs • 2-to-4, 3-to-8, 4-to-16, etc. CMPUT 329 - Computer Organization and Architecture II

  25. y0 = a’b’c’ 3-to-8 Line Decoder y1 = a’b’c y2 = a’bc’ a y3 = a’bc b y4 = ab’c’ c y5 = ab’c y6 = abc’ y7 = abc Decoders CMPUT 329 - Computer Organization and Architecture II

  26. Note “x” (don’t care) notation. Binary 2-to-4 decoder CMPUT 329 - Computer Organization and Architecture II

  27. 2-to-4-decoder logic diagram CMPUT 329 - Computer Organization and Architecture II

  28. Negative Logic 2-to-4 Decoder • Input buffering (less load) • NAND gates (faster) CMPUT 329 - Computer Organization and Architecture II

  29. Decoder Symbol CMPUT 329 - Computer Organization and Architecture II

  30. Complete 74x139 Decoder CMPUT 329 - Computer Organization and Architecture II

  31. More decoder symbols CMPUT 329 - Computer Organization and Architecture II

  32. 3-to-8 decoder CMPUT 329 - Computer Organization and Architecture II

  33. 74x138 3-to-8-decoder symbol CMPUT 329 - Computer Organization and Architecture II

  34. Decoder Cascading 4-to-16 decoder CMPUT 329 - Computer Organization and Architecture II

  35. 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 More Cascading 1 1 0 0 What is the output when the input is 01011 and the decoder is enabled? N4=0,N3=1,N2=0,N1=1,N0=1 0 0 5-to-32 decoder CMPUT 329 - Computer Organization and Architecture II

  36. Decoder applications • Microprocessor memory systems • selecting different banks of memory • Microprocessor input/output systems • selecting different devices • Microprocessor instruction decoding • enabling different functional units • Memory chips • enabling different rows of memory depending on address • Lots of other applications CMPUT 329 - Computer Organization and Architecture II

  37. Programmable Logic Arrays (PLAs) • Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections. • n inputs • AND gates have 2n inputs -- true and complement of each variable. • m outputs, driven by large OR gates • Each AND gate is programmably connected to each output’s OR gate. • p AND gates (p<<2n) CMPUT 329 - Computer Organization and Architecture II

  38. n Input Lines ••• Programmable Logic Array Structure PLA AND Array OR Array •••••• •••••• K Word Lines m Output Lines CMPUT 329 - Computer Organization and Architecture II

  39. R R R R R R R R R +V +V +V +V +V F1 F0 F3 F2 Internal Structure of a PLA Inputs A B C A’B’ AC’ B BC’ AC F0 = A’B’ + AC’ Outputs CMPUT 329 - Computer Organization and Architecture II

  40. a b c d a’ b’ c’ d’ ab’c’ b’c c bc Internal Structure of a PLA Inputs a’bd abd Word Lines F1 F2 F3 Outputs CMPUT 329 - Computer Organization and Architecture II

  41. B BC’ AC Internal Structure of a PLA Inputs A B C OR ARRAY A’ B’ C’ A’B’ AC’ AND ARRAY F0 F1 F2 F3 Outputs CMPUT 329 - Computer Organization and Architecture II

  42. Example: 4x3 PLA, 6 product terms CMPUT 329 - Computer Organization and Architecture II

  43. Compact Representation CMPUT 329 - Computer Organization and Architecture II

  44. PLA Electrical Design • See Section 5.3.5 -- wired-AND logic CMPUT 329 - Computer Organization and Architecture II

  45. Programmable Array Logic (PALs) • How beneficial is product sharing? • Not enough to justify the extra AND array • PALs ==> fixed OR array • Each AND gate is permanently connected to a certain OR gate. • Example: PAL16L8 CMPUT 329 - Computer Organization and Architecture II

  46. Programmable Array Logic (PAL) A PAL is a special case of a PLA in which the AND array is programmable but the OR array is fixed. I1 F1 F4 Outputs F5 An unprogrammed PAL F8 I2 CMPUT 329 - Computer Organization and Architecture II

  47. Programmable Array Logic (PAL) A PAL is a special case of a PLA in which the AND array is programmable but the OR array is fixed. I1 F1 F4 I1I2’ + I1’I2 F5 A programmed PAL F8 I2 CMPUT 329 - Computer Organization and Architecture II

  48. 10 primary inputs • 8 outputs, with 7 ANDs per output • 1 AND for 3-state enable • 6 outputs available as inputs • more inputs, at expense of outputs • two-pass logic, helper terms • Note inversion on outputs • output is complement of sum-of-products • newer PALs have selectable inversion

  49. Designing with PALs • Compare number of inputs and outputs of the problem with available resources in the PAL. • Write equations for each output using VHDL. • Compile the VHDL program, determine whether minimimized equations fit in the available AND terms. • If they do not fit, try to modify the equations or to provide “helper” terms. CMPUT 329 - Computer Organization and Architecture II

  50. Some Questions Is the criterion to minimize a set of functions to implement in a PAL the same that we used for the implementation with individual gates? What is the problem formulation for the implementation of a set of logic functions in a PAL? CMPUT 329 - Computer Organization and Architecture II

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