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Investigation of Floating Body Effects on SOI MOSFET Gate Tunneling Currents

Investigation of Floating Body Effects on SOI MOSFET Gate Tunneling Currents. Authors: M. Bawedin (1) , M. Estrada (2) , D. Flandre ( 1). (2) CINVESTAV, Mexico. (1) Microelectronics Laboratory, UCL, Belgium. Microelectronics Laboratory (UCL) ULIS workshop : 20 March 2003. Objective

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Investigation of Floating Body Effects on SOI MOSFET Gate Tunneling Currents

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  1. Investigation of FloatingBody Effects on SOI MOSFETGate Tunneling Currents Authors: M. Bawedin (1) , M. Estrada (2) , D. Flandre (1) (2)CINVESTAV, Mexico (1) Microelectronics Laboratory, UCL, Belgium

  2. Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003 Objective Study of particular gate current behaviour in SOI MOSFET Outline • Singular Behaviour in inversion • Dominating gate current mechanisms • Body potential rise • nMOS in inversion • pMOS in inversion • nMOS measurements • Dominating gate current mechanisms • Body potential rise • pMOS measurements

  3. Devices under test Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003 Accumulated pMOS Enhancement nMOS • N+ type Polysilicon gate • N+ type drain/source • P type channel (8E17 cm-3) • TOX=4.5nm ; TSI=30nm • N+ type Polysilicon gate • P+ type drain/source • P type channel (1E17 cm-3) • TOX=4.5nm ; TSI=30nm

  4. Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003 Singular behaviour in inversion Inversion case • 0V < VG<1.5V Expected : IG-nMOS > IG-pMOS due to electrons provided by source and drain Observation : IG-nMOS < IG-pMOS • VG>1.5V Observation :pMOS current saturation

  5. Dominating gate current mechanisms Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003 Inversion mode • ECB from Si inversion layer Dominating gate current • EVB from SiO2/Si interface Hole substrate current generated at SiO2/Si interface

  6. Body potential rise Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003 nMOS in inversion

  7. Body potential rise Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003 pMOS in inversion Simplification: quasi-neutral zone in the Si-film Note: Thermal generation is more efficient for the pMOS case (Nch<<)

  8. nMOS measurements Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003 • 0V < VG<2.5V Expected : IG-inversion > IG-accumulation due to electrons provided by source and drain Observation : IG-inversion < IG-accumulation • VG>2.5V Observation : Current saturation in accumulation

  9. Dominating gate current mechanisms Accumulation mode • ECB from N+ polysilicon gate Dominating gate current • HVB from accumulated layer Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003

  10. Body potential rise Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003 nMOS in accumulation

  11. pMOS measurements Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003 Reciprocal case to nMOS • 0V < VG<1.5V IG-inversion >> IG-accumulation • VG>1.5V Current saturation in accumulation By analogy with nMOS case

  12. Conclusion Microelectronics Laboratory (UCL)ULIS workshop : 20 March 2003 In SOI MOSFET’s Generation/Recombination mechanisms Hole and S/D N+ Electron and S/D P+ Floating body effect Body potential increase IG increase and saturation

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