1 / 20

EE 587 SoC Design & Test

EE 587 SoC Design & Test. Partha Pande School of EECS Washington State University pande@eecs.wsu.edu. SoC Physical Design Issues Clock Distribution. Buffered Clock Distribution. Improves precision and Control Distributed buffers Amplify clock signals

koren
Download Presentation

EE 587 SoC Design & Test

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. EE 587SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

  2. SoC Physical Design Issues Clock Distribution

  3. Buffered Clock Distribution • Improves precision and Control • Distributed buffers • Amplify clock signals • Isolate local clock nets from upstream load impedance

  4. Clock Distribution Structures

  5. H-Tree • The primary clock driver is connected to the center of the main “H” structure • The clock signal is transmitted to the four corners of the main “H” • The conductor widths in H-tree structures are designed to progressively decrease as the signals propagate to lower levels of hierarchy. • This strategy minimizes reflections of the high-speed signals at the branching points

  6. Tapered H-Tree • A tapered line, can achieve the same signal characteristics (signal delay and transition time) as the uniform line shown with a smaller total line capacitance. • Tapering a line reduces the coupling capacitance between the signal line and the adjacent ground lines, and, consequently, the total capacitance of the signal line. • Although the line capacitance is reduced, the line resistance is greater, thereby maintaining approximately the same signal characteristics. • A reduction in the line capacitance decreases the dynamic power while an increase in the line resistance decreases the inductive behavior of the interconnect.

  7. Tapered H-Tree (Cont’d) Exponential Uniform

  8. Performance Analysis Uniform Exponential

  9. Performance Analysis (Cont’d)

  10. Clock Power Issues in SoC Design • Different clock rates of the IP blocks

  11. Clock Power Model

  12. Clock Distribution in Regular Structures

  13. Gated Clock • Cg is the latch’s cumulative gate capacitance connected to the clock. Because the clock switches every cycle, Cg charges and discharges every cycle and consumes significant amount of power. Even if the inputs do not change from one clock to the next, the latch still consumes clock power.

  14. Example of Clock Gating

  15. Interfacing Mixed-Timing Domains • Pausible and Stretchable Clocks • Temporarily pause or stretch the receiver’s clock. • Use of Synchronizers • Two-latch synchronizers • Synchronization FIFO • Mixed-clock FIFO

  16. Pausible Clocking

  17. Mixed Timing SoC Asynchronous Synchronous

  18. Mixed-Timing FIFOs

  19. Clock Distribution of DEC Processor • The single 200 MHz clock signal is distributed through five levels of buffering

  20. Clock Distribution in Intel IA-64 Microprocessor

More Related