1 / 14

BEC System Test

This document provides a summary of the goal of tests, test setup, list of tests, ROD crate configurations, and the status of tests for the LARG ROD system in June 2004.

kovacs
Download Presentation

BEC System Test

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Goal of tests Test setup Setup in EMF List of tests Crate configurations Test configurations Status of tests L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 BEC System Test • Slink data transfer • Tests with FEB • Power consumption • ORx sensitivity • ROD in different slots • Summary remarks

  2. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 Goal of tests • Goal of the tests: to learn system aspects of the LARG ROD • Assumed that all boards are debugged • All board-level tests passed • FW and SW finalized • More details: • BEC TF Report posted at LARG/Electronics web page http://atlas.web.cern.ch/Atlas/GROUPS/LIQARGSTORE/Electronics/BEC_TF/report.pdf • BEC test web page http://kurchan.home.cern.ch/kurchan/Bect/bect.html • Note http://home.cern.ch/kurchan/Bect/bectdoc.pdf

  3. L.Kurchaninov, G.Perrot BEC system test CPU TTCvi TTCex TBM INJECTOR PM PC BC, Orbit, L1A Electrical P3: TTC Electrical INJECTOR CRATE TTC Optical Busy Electrical splitter CPU TBM ROD ROD ROD ROD ROD ROS PC SPAC P3: Busy Electrical Slink Optical P3: TTC Electrical FILAR RCC FILAR FILAR ROD CRATE LARG ROD PRR 25 June 2004 Test setup • Location is chosen at LARG EMF: bd. 2175/R-E24 • ROD crate with max. 5 RODs • Injector and TTC crate • Splitters • PC with 3 FILARs for readout • PC for monitoring • FEC and infrastructure for FEB specific tests

  4. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 Setup in EMF Test of ORx sensitivity Test with 3 RODs

  5. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 List of tests

  6. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 ROD crate configurations • Constraints: 5 ROD modules, 12 PUs, 3 FILARs, one Injector module (up to 24 FEBs) • ROD-TM modes: • S (staging) = 2PU, 2 Links • N (normal) = 4PU, 4 Links • The last configuration 5S is not very interesting and will be done later

  7. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 ROD crate configurations to be tested • Basic tests T01, T02 to be done for all possible configurations • Some configurations can not be tested, e.g. T03 (FEB) • For other tests not all configurations are considered as interesting, e.g. T04 (board power) In table: NO = we are not going to test this configuration YES = configuration to be tested

  8. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 Status of tests • Started in Feb. 04. Start-up period was longer than expected • Many upgrades of FW and SW done but no HW modifications were needed up to now. Not to be done

  9. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 T01: Slink data transfer • No Glink cooling, typically T=50C • No TTC synchronization in DSP, no calculations in DSP • 5 Injector signals splitted from 8 to 24 ROD inputs • Incremental data (different for each Injector output) • Acquisition rate from 3 kHz to 32 KHz depending on data verification • Configuration 1N. Runs taken: 100 Mfrg, 46, 50, 562, 115, 226, 716, 746, 3031 - trigger rate up to 100 kHz, acquisition rate 12 kHz • Configuration 1S. Runs taken: 1538 Mfrg, 101, 1633 - trigger rate up to 60 kHz • Configuration 3N. Runs taken: 19 Mfrg, 144 - trigger rate up to 100 kHz, acquisition rate 3 kHz • Configuration 3S. Runs taken: ?? Mfrg, ?? -Trigger rate up to 60 kHz, acquisition rate 3 KHz

  10. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 T03: Tests with FEB • Done in past with 40.00 MHz, no TTC synchronization ~180 Mfrg • QPLL FEB output splitted to 8 ROD inputs (power = -16 dbm) Runs taken: 521 and 3000 Mfrg at each Slink. Trigger rate 100 KHz, acquisition rate 32 KHz (only parity check and half-channel symmetry) • Optical sensitivity measured on 1 ROD ORx at –23.5 dbm with an original signal at –8 dbm (optical splitter and variable attenuator used)

  11. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 T04: Boards power consumption Reports in: http://home.cern.ch/kurchan/Bect/bect.html TM current measured as V drop at 0.01W resistor vs Acq rate. ROD power consumption measured as V drop at 0.001W or 0.01W resistor Extrapolation to 100 kHz: 0.271A • Measured values ~ design values

  12. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 T06: ORx sensitivity Report in: http://home.cern.ch/kurchan/Bect/bect.html • Measured for 3 ROD boards • Example: ROD #FA, ch.1,2 connected directly to INJ, ch.3-8 through splitter • Glink errors for events ~ -17 dbm • Glink errors without events ~ -21 dbm • Long run of 650 Mevts with 1 dbm margin

  13. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 T07: ROD in different slots • The same conditions as in T01 • ROD-TM were moved over slots 7-20. In each position a short run taken with 5-6 Mfrg • In slot 10 a long test of 400 Mfrg was done over night. No errors detected

  14. L.Kurchaninov, G.Perrot BEC system test LARG ROD PRR 25 June 2004 Summary • No fundamental problems with HW, FW or SW found • No HW modifications were needed up to now • Verified by today: • FEB-ROD data transfer • ROD-PU-ROD data path • TM functionality and Slink data transfer • TBM functionality and P3 uniformity • SPAC functionality • Many upgrades of FW and SW done during the tests. Not yet in final shape, under intensive developments • Not all tests done by today, the work is going on. Important: • TTC synchronization • Variable processing time (calcs in DSP) • Histograming and VME bandwidth

More Related