The IEEE 1149.4 std for mixed-signal test

1. The IEEE 1149.4 std for mixed-signal test J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias 4200-537 Porto - PORTUGAL Tel. 351 225 081 748 / Fax: 351 225 081 443 (jmf@fe.up.pt / http://www.fe.up.pt/~jmf)

2. The IEEE 1149.4 standard for mixed signal test • The 1149.4 std defines an extension to 1149.1, to which it adds: • An analog test port (ATAP)with two pins (AT1, AT2) • An internal analog test bus(AB1, AB2) • A test bus interface circuit (TBIC) • The analog boundary modules (ABM)

3. IEEE 1149.4: The TBIC and the ABMs • Interconnect and parametrictests can be carried out throughthe ABMs • Analog test signals may be routed from / to the analog pins to / from the ATAP through the TBIC and the ABMs • The TBIC and the ABM comprise a switching structure and a control structure

4. The test bus interface circuit (TBIC) • The TBIC defines the interconnections between the ATAP (AT1 and AT2) and the internal analog test bus (at least two lines, AB1 and AB2) • The TBIC comprises a switching structure and a control structure

5. TBIC: The switching structure

6. TBIC: Switching structure patterns Main testing conditions

7. Switching assignments for defined instructions (TBIC)

8. TBIC: Control structure

9. The analog boundary modules (ABM) • The ABMs in the analog pins extend the test functions made available by the DBMs • All test operations combine digital (via TAP) and analog test “vectors” (via ATAP) • Each ABM comprises a switching structure and a control structure

10. ABMs: Switching structure

11. ABMs: Switching structure patterns (1) Main testing conditions for analog measurements

12. ABMs: Switching structure patterns (2) Normal mission mode; pin connected to core only.

13. ABMs: Switching pattern requirements

14. ABMs: Control structure

15. The 1149.4 register structure • The 1149.4 register structure is entirelydigital and identicalto the corresponding1149.1 structure

16. The PROBE instruction • The IEEE 1149.4 std defines a fourth mandatory instruction called PROBE: • The selected data register is the BS register • One or both of the ATAP pins connect to the corresponding AB1/AB2 internal test bus lines • Analog pins connect to the core and to AB1/AB2 as defined by the ABM 4-bit control word • Each DBM operates in transparent mode

17. Analog test operations • Principle of operation: • The analog signal is applied to AT1 and the analog response is observed in AT2 • With AT1 connected to AB1, the analog signal may be routed to the internal circuitry or to an analog output pin • Analog responses from the internal circuitry or from an analog input pin are routed to AB2, and observed in AT2

18. Observability of analog (input / output) pins • The signal present at any analog (input / output) pin may be observed at AT2, with (or without) the core connected to the pin

19. Controllability of analog (input / output) pins • The signal present at any analog (input / output) pin may be driven from AT1, regardless of the signal present at the analog input

20. ZD = VT / ITif: • ZV >> ZS6 + ZSB2 • ZV + ZS6 + ZSB2 >> ZD IT ZD V VT Impedance measurement between pin and ground

21. VH ? VL VH ? VL Interconnect testing with 1149.4

22. Functional description of a basic “1149.4 component” • The core circuitry is restricted to • A voltage follower • A logic inverter • The required 1149.4 infrastructure should only support the mandatory instructions

23. Summary description of the 1149.4 infrastructure • Instruction codes (8-bit): • EXTEST: $00 • SAMPLE / PRELOAD: $02 • PROBE: $01 • BYPASS: $FF • Boundary scan register (TDI-TDO, 14-bit): • TBIC (4-bit), ABM analog input (4-bit), ABM analog output (4-bit), DBM digital input (1-bit), DBM digital output (1-bit)

24. Implementation details • The digital test infrastructure and core logic was implemented by Dr. Gustavo Alves in an EPM7128 Altera PLD (2,500 usable gates, 128 macrocells, 84 pin PLCC) • All remaining blocks are implemented using discrete components (ADG452 + MAX4512 analog switches, LM311 comparators, TL081 OpAmp)

25. “1149.4 component”: the digital test infrastructure

26. Altera’s design environment (Max+plus II Baseline)

27. Example description (ABM)

28. ABM: the control structure IF ( !en_clkDR ) THEN DATA = DATA ; CONTROL = CONTROL ; BUS1 = BUS1 ; BUS2 = BUS2 ; ELSIF ( !shift ) THEN DATA = pin_comp; % Capture % CONTROL = GND; BUS1 = GND; BUS2 = GND; ELSE DATA = TDI; % Shift % CONTROL = DATA; BUS1 = CONTROL; BUS2 = BUS1; END IF; TDO = BUS2; • IF ( !en_uptDR ) THEN • D_LATCH = D_LATCH ; • C_LATCH = C_LATCH ; • B1_LATCH = B1_LATCH ; • B2_LATCH = B2_LATCH ; • ELSE • D_LATCH = DATA; % SHIFT -> LATCH -- update % • C_LATCH = CONTROL ; • B1_LATCH = BUS1 ; • B2_LATCH = BUS2 ; • END IF; • D = D_LATCH.q ; • C = C_LATCH.q ; • B1 = B1_LATCH.q ; • B2 = B2_LATCH.q ; • END; TITLE " ABM control register "; SUBDESIGN ABM_CR ( TDI, TCK, en_clkDR, shift, en_uptDR, pin_comp : INPUT; TDO, D, C, B1, B2 : OUTPUT; ) (...)

29. ABM: the switching structure decoder BEGIN TABLE M1, M2, D, C, B1, B2 => SD, SH, SC, SG, SB1, SB2 ; 1,1,0,0,0,0 => 0,0,0,0,0,0 ; % p0 - Completely isolated (CD state) % 1,1,0,0,0,1 => 0,0,0,0,0,1 ; % p1 - Monitored by AB2 % 1,1,0,0,1,0 => 0,0,0,0,1,0 ; % p2 - Connected to AB1 % 1,1,0,0,1,1 => 0,0,0,0,1,1 ; % p3 - Connected to AB1; monitored by AB2 % (...) 1,1,1,1,1,1 => 0,1,0,0,1,1 ; % p15 - Connected to VH and AB1; monitored by AB2 % 0,1,0,0,0,0 => 1,0,0,0,0,0 ; % p16 - Connected to core; isolated from all test circuits % 0,1,0,0,0,1 => 1,0,0,0,0,1 ; % p17 - Connected to core; monitored by AB2 % 0,1,0,0,1,0 => 1,0,0,0,1,0 ; % p18 - Connected to core and AB1 % 0,1,0,0,1,1 => 1,0,0,0,1,1 ; % p19 - Connected to core and AB1; monitored by AB2 % 0,1,1,X,X,X => 1,0,0,0,0,0 ; % p16 - Clause 6 - page 74 % 0,1,X,1,X,X => 1,0,0,0,0,0 ; % p16 - Clause 6 - page 74 % 0,0,X,X,X,X => 1,0,0,0,0,0 ; % p16 - Clause 4 - page 74 % 1,0,X,X,X,X => 0,0,0,0,0,0 ; % p0 - Clause 3 - page 74 % END TABLE;

30. “1149.4 component”: the TBIC switching structure

31. “1149.4 component”: the ABMs switching structure

32. An “1149.4 component”: wire wrapping prototype

33. An “1149.4 component”: printed circuit board Selection of VTH (internal / external) Notes: 1) The ABM comparator inputs in this board differ from the standard (VTH is connected to the + input). 2) VG / VTH may be applied externally (internal value of VG is 0 V) Selection of VG (internal / external)

34. Proposed experiments: observability + controllability • Two experiments will be demonstrated using the wire-wrapping “1149.4 component”: • The waveform at the analog output pin will be observed at AT2, when the analog input is driven by a sine wave • The waveform at the analog output pin will be driven from AT1 (a square wave), instead of the sine wave coming from the internal circuitry

35. Observing an analog input / output pin at AT2 • PROBE is the current instruction, the input ABM connects the pin to the core, the output ABM connectsthe pin to the coreand to AB2, AB2 is connected to AT2

36. Observability test code segment AN_IN • Recommendation: Write the JTAGer testsegment enablingthe observability of the analog output as shown at right AN_OUT AT1 AT2 AN_IN AN_OUT AT1 AT2

37. Observability test code (demo component) ! Observability demo using the 1149.4 component start: seltap0; rst; state irshift; ld cnt,8d; ! IR has 8 bits nshfcp 40h,80h,C0h; ! Instr. S/P and infra-structure check jerr tap-error; ! Abort test in case of TAP error state drshift; ld cnt,14d; ! 4 TBIC + 2x4 ABMs + 1 DBM + 1 DBM nshf 2020h; ! 0001(TBIC)- 0000(ABMin)- 0001(ABMout)- 00(DBMs) state irshift; ld cnt,8d; nshf 80h; ! Instr. PROBE tms1; ! Update-IR end: halt; ! Stop here if everything is OK tap-error: halt; ! Stop here if the TAP is faulty Before thebreakpoint After thebreakpoint << Breakpoint

38. Controlling an analog output pin from AT1 • EXTEST is the current instruction, the input ABM disconnects the pin from the core,the output ABM disconnects the pin from the coreand connects it to AB1, AB1 connects to AT1

39. Controllability test code segment AN_IN • Recommendation: Write the JTAGer testsegment enablingthe controllability (plus observability) of the analog output as shown at right AN_OUT AT1 AT2 AN_IN AN_OUT AT1 AT2

40. The SCAN STA400 (1149.4 analog test access device) • Features (from the data sheet): • Compliant to IEEE 1149.1 and 1149.4 • Analog mux / demux either dual 2:1or single 4:1 • Samples up to 9 analog test points • Includes CLAMP and HIGHZ instructions • TRST input • Input range from -0,5 V to +6,5 V

41. SCAN STA400:Operating modes

42. SCAN STA400:Functional information • CE/CEI distinguish between the two main operating modes (analog sample, mux / demux)

43. SCAN STA400:Template to determine the BSR contents 1- Instruction 2- ABMs: switches, switching pattern, control word 3- TBIC: switches, switching pattern, control word

44. Demonstration board #1: Stand-alone STA400 CEI 0 CE 1 A C1 0 C0 AT1 Notes: 1) The internal 7805 generates the +5 V power supply 2) The operating mode is selected via a set of built-in jumpers 0 M 0 ATAP connections The built-in current source is adjustable JTAGer-compatible TAP connections  is 0, is 1 SCANSTA400 analog I/O pins +12 V / GND power supply

45. Demonstration board #2: STA400 and BCT8244 • The STA400 andthe BCT8244 arein the same chain • The BCT8244 is able to control theSTA400 • Parametric andfunctional tests are possible

46. Schematic diagram

47. Demonstration board #2 Adjustable current source DIP switches that control the BCT8244 octal outputs National Semiconductor SCANSTA400 SN74BCT8244 BST octal (TI SCOPE family) Connectors and space available for add-on boards

48. Add-on boards

49. Experiment #1: Control A01 via the BCT8244 scan octal STA400 BCT8244 s: sine A0 A01 s/p p: pulse A1 DIP switch C0 1Y1 TDI TDO

50. Experiment #2: Functional test (observe A0 at AT2) STA400 BCT8244 s: sine A0 A01 s/p p: pulse A1 DIP switch AT2 TDI TDO