1 / 22

Energy Benefits of Reconfigurable Hardware for Use in Underwater Sensor Nets

Energy Benefits of Reconfigurable Hardware for Use in Underwater Sensor Nets. Bridget Benson, Ali Irturk , Junguk Cho, and Ryan Kastner Computer Science and Engineering Department University of California, San Diego. Motivation: Monitoring in Moorea.

lee
Download Presentation

Energy Benefits of Reconfigurable Hardware for Use in Underwater Sensor Nets

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Energy Benefits of Reconfigurable Hardware for Use in Underwater Sensor Nets Bridget Benson, Ali Irturk, Junguk Cho, and Ryan Kastner Computer Science and Engineering Department University of California, San Diego

  2. Motivation: Monitoring in Moorea • Establish monitoring sites in lagoons and on fore reefs surrounding Moorea • Response variables measured: • Weather • Tides, Currents and Flows • Ocean Temperature & Color • Salinity, Turbidity & pH • Nutrients • Recruitment & Settlement • Size & Age Structure • Species Abundance • Community Diversity

  3. Vision for Underwater Networking in Moorea Viapahu Lagoon UC Gump Research Station L Legend Drogues Stingray Local Area Underwater Network Acoustic Link ReefPole AquaNode

  4. Need a Low-Cost, Energy Efficient Underwater Acoustic Modem • Energy Efficiency is extremely important to maximize battery and deployment lifetime • Cost is extremely important for dense deployment • Commercial Modems • Too Expensive ($5000-$10000) • Designed for long-range sparse systems, not small, dense sensor nets • Research Modems • WHOI MicroModem is still the best available for ecological sensing, but can we further reduce costs and energy consumption?

  5. AquaModem Pelican case • Hardware • TI 6713 DSP • Sonatech transducers • Homemade power amplifier • Software • Direct Sequence Spread Spectrum signaling based on Walsh waveforms • Matching Pursuits Algorithm for detection and channel estimation Power Amplifier Sonatech Transducer 24 KHz center freq. TI 6713 DSP Successfully tested at Westlake Village lake at 70m range Power Amplifier Pelican case R. Iltis et. al. “An Underwater Acoustic Telemetry Modem for Eco-Sensing”, MTS/IEEE OCEANS 2005

  6. Transmitted Signal 1 1 -1 1 -1 -1 -1 -1 -1 1 -1 1 1 1 1 1 -1 1 -1 -1 -1

  7. AquaModem Design Parameters

  8. Matching Pursuit Core Matching Pursuit Core arg min i Note: 112 samples/symbol + 112 samples for channel clearing. Matching Pursuit Core Matching Pursuit Core AquaModemReceiver Specification Generalized multiple hypothesis test (GMHT)

  9. Tx Boat Tx Boat Rx Boat AquaModem Tests in Moorea

  10. Results summary • Symbol Error Rate < 1% • Distances up to 500m • Hardware Platform Energy Consumption Dominates for lowtransmit power • Motivates need to try other hardwareplatforms for reduced energy consumption

  11. AquaNode Battery • Deploy ad hoc wireless underwater networks around island • Transmit data to/from underwater sensors • Aquanode requirements: • Low cost, low power wireless modems • Associated networking functionality • Plug and play interface with variety of sensors • Near real-time data and adaptive sampling Software Defined Acoustic Modem Transparent View Transducer

  12. . . . . . . RS232 Controller A/D D/A D/A Transducer or Hydrophone inputs FPGA Matching Network and Power Amp Daughtercard A/D CTD Sensor AquaNode Hardware Platform • Ideal: One piece of hardware for any sensor and scenario • Hardware is wirelessly updatable: no need to retrieve equipment to update hardware for changing communication protocols, sampling, sensing strategies

  13. Matching Pursuits Algorithm • Used for channel estimation and detection • Channel Estimation calculates delay and attenuation parameters for each path • Applies to any direct sequence spread spectrum signal • Provides increased noise immunity for improvement in signal detection • Highly parallelizable (idealcandidate for a hardware solution)

  14. Inputs and Outputs • Input (r, S, A, a) • Output (f) • R: received signal vector (224 x 1) • S: signal matrix (224 x 112) • 224 rows matching received vector size • 112 columns as shifted versions of 112 chip waveform • A: Hermetian Matrix (224 x 224) • SHS • a: 1divided by diagonal elements of A (112x1) • Used to eliminate division operations • f: Estimated channel coefficients • Based on the number of estimated paths

  15. MP( ) r, S, A, a for 1 i = 1, 2, …, N S // compute matched filter (MF) outputs 2 ¬ 0 T V S r i i 3 ¬ f 0 i 4 ¬ g 0 i end for 5 6 ¬ q 0 0 // do successive interference cancellation for 7 = 1, 2, …, j N f // update MF outputs 8 ¬ - - j j 1 V V f A q q - - j 1 j 1 9 for = 0, 1, …, k - N 1 S 10 ¬ j g v a k k k 11 ¬ j * Q ( v ) g k k k end for 12 13 ¬ q arg max { Q } j k ¹ k , k q ,..., q - 1 j 1 14 ¬ f g q q j j 15 end for return 16 ( ) f

  16. MP( ) r, S, A, a for 1 i = 1, 2, …, N S // compute matched filter (MF) outputs 2 ¬ 0 T V S r i i 3 ¬ f 0 i 4 ¬ g 0 i end for 5 6 ¬ q 0 0 // do successive interference cancelation for 7 = 1, 2, …, j N f // update MF outputs 8 ¬ - - j j 1 V V f A q q - - j 1 j 1 9 for = 0, 1, …, k - N 1 S 10 ¬ j g v a k k k 11 ¬ j * Q ( v ) g k k k end for 12 13 ¬ q arg max { Q } j k ¹ k , k q ,..., q - 1 j 1 14 ¬ f g q q j j 15 end for return 16 ( ) f Matching Pursuits Core • Goal: Map matching pursuits to reconfigurable device • Parameterizable – number of samples, data representation System Design Tools Reconfigurable System

  17. Design Space Tradeoffs • Levels of Parallelism • Parallelism Area Execution Time • Fully parallel design has 112 filter and cancel blocks • Fully serial design has 1 filter and cancel block reused 112 times • Bit Widths • Bits Accuracy Area • 8-10 bits sufficient for accurate channel estimation • FPGA Device Selection • Variations in amount of resources • Has large effect on power and energy consumption of design

  18. Area, Timing and Throughput Results

  19. Power and Energy Comparison

  20. Hardware Platform Comparison

  21. The Next Generation

  22. Questions?

More Related