Keith Bergevin Senior Design Engineer 4234 54 th St., Bldg 620 Sacramento, Calif. 95652-1521

1. Defense Microelectronics Activity Rapid Obsolescence in Recent Designs – Is There a Solution? Keith Bergevin Senior Design Engineer 4234 54th St., Bldg 620 Sacramento, Calif. 95652-1521 Phone: (916) 231-1652, Fax: (916) 231-2818 email: bergevin@dmea.osd.mil http://www.dmea.osd.mil

2. Presentation Roadmap • Why are recent generation designs highly susceptible to obsolescence? • What options are available? • ASIC redesign methodologies • Ensuring a complete solution

3. Why are Recent Generation Designs Becoming an Enormous Problem? • Consist primarily of ASIC devices • Virtually sole source • Custom ASICs have limited supply – typically one fabrication run • Unique design eliminates component supply “sharing” • Very difficult to redesign • High density, complex devices • Design documentation is critical but often deficient • No correlation between part numbers and design functions

4. What Options are Available? • Direct FFF replacement? No! • ASICs perform specific functions – with the exception of FPGAs, finding an equivalent device number will not suffice • Exhaustive database search for second source? No! • Custom designs render search of other programs for equivalent devices useless • The only remaining option – various levels of redesign • Component, board, or system redesign

5. The Dilemma of ASIC Redesign • Recent program upgrades experienced obsolescence within two years – why go through the same process? • Valid argument - Without a change in approach, the solution will again be temporary • Insufficient data exists on the obsolete module, resulting in prohibitively expensive redesign proposals • Unfortunately, this is a common occurrence • Where does this lead us?

6. The Prudent Way Out of This Mess • The Previous slides have established the following: • The “quick & easy” solutions do not exist • A redesign approach is the only remaining option • Insufficient documentation results in difficult and costly redesigns • Option (2) was recently implemented without eliminating obsolescence • An ideal solution would include the following: • Tools and methodologies to reduce NRE redesign costs • Implement designs with better DMS immunity • Realize obsolescence is inevitable - apply methodologies that enable device re-targeting without costly redesign

7. DMEA’s ASIC Redesign Approach • Apply cutting edge tools & methodologies to accurately characterize legacy component • Scrutinize components to select least vulnerable • DMEA flexible foundry • Select components commonly used by industry to provide greater assurance of future availability • Provide complete, verifiable, vendor-independent documentation • VHDL, Verilog, EDIF, etc.

8. Developing an Accurate Redesign Specification – AnExtremely Difficult Requirement • Many obsolete ASICs contain up to 1M gates • ASIC devices perform unique functions • Vendor data sheets provide no functional descriptions • Specific component number provides no functional information • Package size, type, & pin-out vary greatly • Virtually impossible to have 100% test coverage • Board level test programs typically cover small subset of ASIC functions

9. DMEA Developments in the Specialty of Device Characterization • Hardware Modeling: A novel approach to ASIC redesign • Method of interfacing actual legacy silicon into simulation environment • The device becomes a logic model which is instantiated into the VHDL design for simulation • Enables creation of a fast, efficient and 100% accurate simulation model of the legacy device • Enables direct functional comparison of Legacy vs. redesigned component

10. Hardware Modeler Configuration DeviceAdapter HardwareModeler High-end Workstation

11. Prototype Development 1. Synthesize VHDL model to Field Programmable Gate Array (FPGA) 2. Migrate test vectors to board or chip level tester • Vectors translated from VHDL test benches 3. Apply test vector set to legacy device and FPGA prototype 4. Compare vector output files 5. Test prototype at customer facility

12. Fabrication Options • DMEA Flexible Foundry • Form, fit, function replacement via commercial devices • Re-Target VHDL to ASIC with matching footprint • FPGA to ASIC conversion • FPGA die repackaging • Replace legacy device with FPGA • Low-cost approach for small quantities • May require modification to board layout

13. Summary • Recent generation designs are extremely susceptible to obsolescence • Database and other tracking tools largely ineffective in finding replacement devices • DMEA is maintaining a leadership role in applying tools, techniques, and expertise to combat obsolete ASICs • Adhere to sound DMS redesign practices to ensure long term cost-effective solutions