Booster Cogging Upgrades Craig Drennan , Kiyomi Seiya , Alex Waller

1. Booster Cogging Upgrades Craig Drennan, KiyomiSeiya, Alex Waller

2. RF cogging to momentum cogging current cogging-RF cogging momentum cogging hardware requirements Replace cogging board with new board switch to MFC board status

3. Why do we need cogging? Time Gap for the extraction kicker 2nd pulse 1st pulse MI 1 revolution Booster is going to extract 12 pulses every 15Hz for the Nova operation. Booster notch position supposes to synchronize to the MI injection.

4. Move notch creation earlier 1st pulse 2nd pulse Intensity B field Notch @ 400msec @ 7msec The notch was created at 7msec for the 2-12th pulse. Creating the notch at lower energy can reduce beam loss in the Booster.

5. Bucket difference between Booster and MI MI inj. freq. : 52811400Hz The bending field in the Booster, injection energy, timing, rf feedback …..are changing from pulse to pulse and bucket position at extraction is not constant.

6. Current cogging – RF cogging – (1) The revolution frequency difference between reference cycle and cycle with B field error. Final bucket position 2 1 Notch @ 7msec -Predicts final bucket position by measuring Gradient1, 2. -Sends RPOS offset which is required for the frequency changes.

7. Current cogging – RF cogging – (2) Final bucket position +/- 10 buckets RPOS offset Transition energy

8. Momentum cogging B+dB Fixed with RPOS feedback Changed by dipole corrector Dipole corrector: 0.009[T-m] @ 24.4[A] (Assuming 10[A] change ) B field error ~1% can be compensated. Keeps the orbit centered and saves aperture. Has two feedback loops for frequency and RPOS .

9. Dfrevwith RF cogging and Momentum cogging

10. Cogging board RF cogging (after 7msec) ΔCn-1[turn], ΔCn[turn] Calculates gain for RPOs offsets. Calculates gain for corrector current. B dot Counts: ΔC[turn] diff_rev_ freq FPGA DSP Radial offset DAC MI rev marker Booster rev m Notch pulse DAC Dipole correctors RPOS feed back Momentum cogging (before 7msec)

11. Control for the dipole corrector offseet C473 H-short01 DAC Current curve 1 short-H-1 Σ PS Amp/msec Cogging MFC DAC Need cable, amplifier and timing for all 48 corrector.

12. Switching to new board Current Cogging board MFC board DSP SHARC FPGA ALTERA

13. Multi‐cavity Field Control (MFC) Module AD/LLRF group has been developing this board for the last 10 years. It is similar to the current cogging board. (VXI based ALTERA FPGA) Current cogging board has one spare. Some parts are no longer available. Spec: 32 * 12-bit, 65MS/S ADC input channels including 2 DC coupled channels 1 * 14-bit105MS/S ADC input channel 4 * 14-bit 260 MS/S DAC channels configurable as AC or DC coupled 1 * 8 output clock divider chip with a 1.6 GHz max external clock input 1 * External Aux clock input (LVCMOS) to FPGA and/or DAC 2 * Front panel TTL trigger inputs

14. Booster LLRF VXI crate 1: slot 0 2: beam power 3: Digital freq. reference 4: Para Phase 5: Cogging 6: pulse to Cogging 1 2 3 4 5 6

15. Status of the new board Resource Manager Booster LLRF VXI crate frequency curve -Logical address (SC) Beam power (SC) Para phase (SC) RF Cogging (SC) new cogging with MFC board (DC) FPGA and DSP codes setup environments on PC. header, library, compiler….. Slot 0 card new Motorola compiler Communication between slot 0 card and DSP old: slot 0  shared memory  DSP new: slot 0  -------------------  DSP

16. Future Plan RF cogging on the new board. (before shutdown) Setup offset control for dipole corrector. (during shutdown) Add momentum cogging. (during shutdown) Beam studies and simulations. (on going)