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Implementation of Turbo Code in TI TMS320C8x

Implementation of Turbo Code in TI TMS320C8x. Hao Chen Instructor: Prof. Yu Hen Hu ECE734 Spring 2004. Turbo Codes. Shannon established the fundamental theory about the transmission rates in digital communication system

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Implementation of Turbo Code in TI TMS320C8x

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  1. Implementation of Turbo Codein TI TMS320C8x Hao Chen Instructor: Prof. Yu Hen Hu ECE734 Spring 2004

  2. Turbo Codes • Shannon established the fundamental theory about the transmission rates in digital communication system • The practically feasible channel utilization is almost closed to the theory communication capacity limit; • The lower complexity of decoder is gained through two separately decoder compared with one decode; • Turbo Codes play an important role in the next generation communication system

  3. Encoder of Turbo Code • Parallel concatenation convolutional codes (PCCC) • Output sequence has near uniform distribution probability with well designed interleaver.

  4. Convolutional (RSC) Encoder • Generator matrix of a rate ½ RSC code can be defined:

  5. Viterbi Algorithm for Convolutional Code P(i,t) : The min cost when the state is i at the time t. S(i, t): The path from time 1 to t corresponding to the P(i,t).

  6. A Posteriori Probability Algorithm (APP) • Minimize the symbol error probability • The code is decided by the log-likelihood ratio • Original infromation at time t : The received sequence from time 1 to time T

  7. Iterative algorithm of Turbo Code • Two component decoders serially concatenated via an interleaver • The priori probabilities obtained from first decoder is used at the second decoder

  8. Iterative algorithm of Turbo Code • Use priori information to caculate • Forward recursion: t=1, 2, …, T • Backward recursion: t=T, T-1, …, 2, 1 • log-likelihood ratio

  9. Implementation in TMS320C8x • Modify the algorithm to save memory • Apply two decoders in one DSP; (time share) • Map the algorithm to utility multiprocessor of TMS320C8x more efficiently;

  10. Memory location analysis Step 1: Receive the code sequence; get the for decoder1.

  11. Memory location analysis Step 4: Calcualte of decoder 1 with

  12. Implement forward recursion • Map forward recursion to four parallel processors of TMS320C8x • No additional memory is needed to store temporary value

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