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ECE 353 Introduction to Microprocessor Systems. Michael G. Morrow, P.E. Week 10. Decoding Exercise. Using only a single 74HC138 decoder, place a 32Kx8 RAM at 00000h and a 64Kx8 ROM at F0000h. Decode as exhaustively as possible.
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ECE 353Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 10
Decoding Exercise • Using only a single 74HC138 decoder, place a 32Kx8 RAM at 00000h and a 64Kx8 ROM at F0000h. • Decode as exhaustively as possible. • Draw memory map, show fold-back and block sizes (decoder granularity).
Topics • I/O port basics • I/O ports with MSI devices • P compatible devices • Address decoding for isolated and memory-mapped I/O • Conditional I/O • 80C188EB integrated I/O unit • 82C55A PPI
I/O Port Basics • I/O subsystems allow CPU to interact with the outside world • Input, output, and combined I/O blocks • Input ports • Byte • Word • Output ports • Byte • Unconditional I/O
MSI I/O Ports • Medium Scale Integration (MSI) circuits are available to construct ports • Simple byte input ports can be constructed from… • Octal buffers • Octal latches • Simple byte output ports can be constructed from octal latches
P Compatible I/O Devices • Complex I/O devices typically require complex interface and control logic • P compatible I/O devices have the necessary logic built in to the device itself • Interface designed to be reasonably compatible with many microprocessor buses • Need to add decoding/selection logic • Examples • Device controllers • Used to control complex I/O devices (LCD, disk drives, etc.) • Generic model • Example – Hitachi HD44780U LCD Controller
I/O Address Decoding • I/O address decoding determines the logical location of the I/O device • Isolated I/O • Memory-mapped I/O • Input vs. output ports • Same address does not guarantee same function! • Device select pulses • Wait states • Using the CSU with I/O devices
I/O Address Decoding (cont.) • PAL/PLA Decoders • Nonspecific I/O strobes • /IOW • /IOR • Linear selection • Conventional decoders • Device select strobes • Cascading
Conditional I/O • Conditional vs. unconditional transfers • Hardware example • Polling • Overhead • Flags / semaphores • Wait loops • Timeouts • Software example • Possible race condition
80C188EB Integrated I/O Unit • Port 1 Functions • Port 2 Functions • Bidirectional pin structure • Synchronizer • Programming • Port Control Register • Port Direction Register • Port Data Latch Register • Port Pin State Register
82C55A Programmable Peripheral Interface (PPI) • LSI device providing 24 bits of I/O • Logical organization • Block diagram • Software configurable ports • Three modes of operation • Mode 0 • Basic Input/Output ports • Mode 1 • Strobed Input/Output • Mode 2 • Bidirectional data bus • Bit set/reset capability
Real-World Example • Interface the MAX158 8-bit, 8-channel ADC to the 80C188EB • Hardware interface • Use /GCS0 at I/O address 1000h (CSU) • Poll conversion status using Port 2. • P2CON / P2DIR / P2LTCH / P2PIN • Software interfacing • Write a procedure that does an ADC conversion and then reads the ADC value using mode 1 • Input: AL = ADC input channel to use (0-7) • Output: ADC value returned in AL • What about mode 0? Timing?
Wrapping Up • Homework #5 due Friday, 11/9/2001
Conditional I/O Exercise Write a procedure to read data from an input device like the hardware example. Assume that the flag is a READY signal (active high). If the device does not become ready after 1 million polling attempts, return with the carry flag set, otherwise, return with the data in AL and the carry flag cleared.
