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ABC130 Testability and SEU Protection Reset eFUSE

ABC130 Testability and SEU Protection Reset eFUSE. ABC & HCC FDR. SEU Protection . The baseline about this design is to NOT adopt systematic triplication because of the power cost. -> Only fraction of the design is protected

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ABC130 Testability and SEU Protection Reset eFUSE

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  1. ABC130 Testability and SEU ProtectionReseteFUSE ABC & HCC FDR

  2. SEU Protection • The baseline about this design is to NOT adopt systematic triplication because of the power cost. • -> Only fraction of the design is protected • A part of the justification is because we believe that SEU occuring on some parts of the chip will only cause wrong or lost packets

  3. SEU Protection • The triplication is used to protect the static configuration and bias registers • We want to avoid “locked” chips btw. 2 resets • It is believed that the optimum SEU protection will be proposed for the final version of this chip, after irradiation campaigns and real operation with radiation field.

  4. Not Prot. Flag Tr. Watchdog “ABCN13” SEU protections Tr. Addr. FIFO Control Tr. Packet FIFO Control Tr. CFG registers Tr. Bias registers Tr. Reset command Tr. Trigger commands

  5. SEU Protection TMR (triplication, 3 clock trees)* • Configurationregisters (with gated clock to save power) • Bias & Threshold Trim DAC Registers • Internal L0 Trigger Counter • (All) FIFO Pointer controllers • (The Pipeline and RAM addressing are not protected) • R3 and L1 Trigger Signals decoding • L0 Trigger and Reset Commands *Triplication script developed by Filipe SOUSA, CERN doctorant, University of Porto

  6. SEU Protection Watchdogs • ABC readout function is protected against DCLs stuck (busy state) by watchdogs • The “Top” sequence for readout produces a flag in case of SEU detected (wrong state) otherwise the consequence of a SEU is packet delayed (not a problem) or packet loss

  7. SEU Protection WHAT ABOUT THE READOUT Block? • No TMR on the readout and serializer block (except the interface FIFOs address control) • Can the readout&serializer be stuck forever (btw. 2 SoftReset) ? (My answer actually is No) • Some of the answers rely on simulations with SEU upset insertion (some exercises done but very time consuming)

  8. SEU Protection SEU events counter (not implemented today) Trim DAC registers SEU detection (not implemented today) Read Sequencer SEU detection Analogue Bias registers SEU detection Configuration registers SEU detection

  9. ABC130 Testability • Scan Path Insertion automatic with the P&R tools (adds 5 pads on the “right” side of chip) • The mask register can be used as a fix pattern hit generator • The hit pattern at the input of pipeline can be readout through 32-bits addressable registers

  10. ABC130 Testability • The chip reacts (sends a packet) • After a read register command (ie.indept of triggers) • After a R3L0ID or L1L0ID with data packets • It can be “physics” packets (but with unknown hit distribution) if the L1Buffer has not been filled with real hits (no L0) • Or No-Data packets if the L1Buffer is prefilled by sending a group of L0 and all channels MASK sets

  11. ABC130 Reset • Some initial statement was that with the regulator control the ABC130 will be powered only when clocks are applied (through the HCC) : all parts with sync Reset except as shown COM-L0 COM DMUX L0 R3_L1 R3L0ID PowerUpReset (async) DMUX L1L0ID + Ext. HardReset (async) Command Decoder SyncRstb COM SoftResetCommand Resets logic (sequencers FIFO etc …) Reset all config. registers

  12. ABC130 Reset • The softReset command should not reset to default the various configuration registers (specs) : the following change will be implemented Guarantees the default state at power up if no clock (but sens. to SEU) COM-L0 COM DMUX L0 R3_L1 R3L0ID PowerUpReset (async) DMUX L1L0ID + Ext. HardReset (async) Async Reset in all config. registers Command Decoder SyncRstb COM SoftResetCommand Resets logic (sequencers FIFO etc …)

  13. eFUSE option • One of the read only register is predefined as an eFUSE register (32 bits) with a chip identifier • Constraint : 3.3 V supply required during Fuse process, 3 dedicated pads (OK) VDDD 3.3V Pulse GND

  14. eFUSE option • Additional Constraint : 3.3 V supply HAS TO BE connected to VDD when not used (default) VDDD 3.3V Pulse GND Means have this additional local (on-chip) bonding when on hybrid

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