ECE 353 Introduction to Microprocessor Systems

1. ECE 353Introduction to Microprocessor Systems Discussion 9

2. Topics • Memory System Design • Q&A

3. Problem: ADuC7026 Memory System Assume that an unlimited supply of 16k x 4 SRAMs are available. Build a 32k x 16 SRAM bank for the ADuC7026 external memory interface that is byte writable. Add logic so that the memory bank is at base address 0x10000000, and is decoded exhaustively.

4. Problem: ADuC7026 Memory System

5. Answer – Key Factors • SRAM organization: • x 4 : impacts # chips per bank • 16K : impacts # banks • Byte writable: affects decode logic (need more CE’s). • Location in memory map: affects decode logic, which /MSx to use.

6. Answer – Organization • SRAM organization: 16K x 4  32K x 16 • Chips per bank: • Number of banks: • Total: 16 bits / 4 bits = 4 Thus, we need banks that are four chips wide. 32K / 16K = 2 Thus, we need 2 banks. 2 banks * 4 SRAMs/bank = 8 SRAMs

7. Answer – SRAM Signals • What impact does the 4-bit data bus of the SRAMs have on the number of address lines they need? • None. There are 16K “words” (4-bit wide in this case) in the part, requiring 16K worth of address lines. • SRAM address bits: • 16K is 214 , so we need fourteen address lines going to the SRAMs, A13:0. • (Note: since the bus width is 16-bits, the address lines are actually one higher than the pin name, i.e., pin A0 is actually address line A1.) • SRAM data bits: need D15:0 – connect in groups of four to the SRAMs in each bank. • SRAM control signals: • /WE – connect to /WS • /OE – connect to /RS • /CE – connect to /CSxx signals from decode logic

8. Answer – Decoding • What is the address range of this memory? • Overall range: • Bank ranges: • Decode signals: 0x10000000 – 0x1000FFFF 0x10000000 – 0x10007FFF 0x10008000 – 0x1000FFFF /MS0 (see p. 79 in ADuC data sheet) A15, A14 (actually is A16, A15) /BHE, /BLE

9. Answer – Decoding

10. Answer – Diagram

11. Answer – Diagram

12. Questions?