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A 12-BIT HIGH PERFORMANCE LOW COST PIPELINE ADC

A 12-BIT HIGH PERFORMANCE LOW COST PIPELINE ADC. H. P. Le, A. Zayegh, J. Singh School of Electrical Engineering Victoria University, Australia 2003 IEEE ICECS-2003 研 究 生：許庭碩 學 號： 98662005 指導教授：陳勛祥. Outline. 1 、 Abstract 2 、 Traditional Flash ADC Architecture

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A 12-BIT HIGH PERFORMANCE LOW COST PIPELINE ADC

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  1. A 12-BIT HIGH PERFORMANCE LOW COST PIPELINE ADC H. P. Le, A. Zayegh, J. Singh School of Electrical Engineering Victoria University, Australia 2003 IEEE ICECS-2003 研 究 生：許庭碩 學 號：98662005 指導教授：陳勛祥

  2. Outline 1、Abstract 2、Traditional Flash ADC Architecture 3、Pipeline ADC Architecture 4、4-bit Modified Flash ADC 5、Noise Analysis 6、Conclusion

  3. Abstract • 2.5v 12-bit high performance and low cost pipeline ADC. • A modified flash ADC was used to reduce the device complexity and attaint lower system power consumption. • At operating frequency of 400 MHz， consumes a total power of 47.7mW.

  4. Outline 1、Abstract 2、Traditional Flash ADC Architecture 3、Pipeline ADC Architecture 4、4-bit Modified Flash ADC 5、Noise Analysis 6、Conclusion

  5. Flash ADC Architecture Comparator : 45 Comparator : 18

  6. Outline 1、Abstract 2、Traditional Flash ADC Architecture 3、Pipeline ADC Architecture 4、4-bit Modified Flash ADC 5、Noise Analysis 6、Conclusion

  7. Pipeline ADC Architecture 0.414 1.414 1 001

  8. Outline 1、Abstract 2、Traditional Flash ADC Architecture 3、Pipeline ADC Architecture 4、4-bit Modified Flash ADC 5、Noise Analysis 6、Conclusion

  9. 1 0 C4 C6 B1 4-bit Modified Flash ADC 16Vref 5Vref 0 1 1 0 0 10 1 0

  10. 1 0 C4 C6 B1 4-bit Modified Flash ADC 16Vref 9Vref 1 0 1 0 0 10 1 0

  11. Outline 1、Abstract 2、Traditional Flash ADC Architecture 3、Pipeline ADC Architecture 4、4-bit Modified Flash ADC 5、Noise Analysis 6、Conclusion

  12. Noise Analysis • At 400MHz sampling frequency, noise analysis of the 12-bit pipeline ADC. • Noise analysis of Resistor, Coarse ADC, Inter-stage SHC, Sub-DAC and Inter-state Amplifier.

  13. Noise Analysis Inter-state Amplifier Inter-stage SHC Coarse ADC Sub-DAC

  14. Noise Analysis

  15. Outline 1、Abstract 2、Traditional Flash ADC Architecture 3、Pipeline ADC Architecture 4、4-bit Modified Flash ADC 5、Noise Analysis 6、Conclusion

  16. Conclusion DNL:-0.6~0.6 INL:-0.5~0.5

  17. Conclusion

  18. References • A. Stojcevski, H. P. Le, A. Zayegh, and J. Singh,"Flash ADC Architecture," Accepted for Publicationm in IEE Electronic Letters Journal, Feb. 2003. • A New Low Power Flash ADC UsingMultiple-Selection Method Wen-Ta Lee, Po-Hsiang Huang, Yi-Zhen Liao and Yuh-Shyan Hwang • H. P. Le, A. Zayegh, and 1. Singh, "A High-speed • Low-Power CMOS Comparator with IO-hit resolution," Proceedings of the Founh Intemtional Conference on Modelling and Simulation (MS'02J, Australia, pp. 138 -142,2002.

  19. THE END Thank you!!

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