EE466: VLSI Design

1. EE466: VLSI Design Power Dissipation

2. Outline • Motivation to estimate power dissipation • Sources of power dissipation • Dynamic power dissipation • Static power dissipation • Metrics • Conclusion

3. Need to estimate power dissipation Power dissipation affects • Performance • Reliability • Packaging • Cost • Portability

4. Where Does Power Go in CMOS?

5. Node Transition Activity and Power • Due to charging and discharging of capacitance

6. Activity factors of basic gates • AND • OR • XOR

7. Dynamic Power dissipation • Power reduced by reducing Vdd, f, C and also activity • Asignal transition can be classified into two categories • a functional transition and • a glitch

8. Glitch Power Dissipation • Glitches are temporary changes in the value of the output – unnecessary transitions • They are caused due to the skew in the input signals to a gate • Glitch power dissipation accounts for 15% – 20 % of the global power • Basic contributes of hazards to power dissipation are • Hazard generation • Hazard propagation

9. Glitch Power Dissipation • P = 1/2 .CL.Vdd . (Vdd – Vmin) ; Vmin : min voltage swing at the output • Glitch power dissipation is dependent on • Output load • Input pattern • Input slope

10. Glitch Power Dissipation • Hazard generation can be reduced by gate sizing and path balancing techniques • Hazard propagation can be reduced by using less number of inverters which tend to amplify and propagate glitches

11. Short Circuit Power Dissipation • Short circuit current occurs during signal transitions when both the NMOS and PMOS are ON and there is a direct path between Vdd and GND • Also called crowbar current • Accounts for more than 20% of total power dissipation • As clock frequency increases transitions increase consequently short circuit power dissipation increases • Can be reduced : • faster input and slower output • Vdd <= Vtn + |Vtp| • So both NMOS and PMOS are not on at the same time

12. Static Power Consumption Wasted energy … Should be avoided in almost all cases

13. Static Power Dissipation • Power dissipation occurring when device is in standby mode • As technology scales this becomes significant • Leakage power dissipation • Components: • Reverse biased p-n junction • Sub threshold leakage • DIBL leakage • Channel punch through • GIDL Leakage • Narrow width effect • Oxide leakage • Hot carrier tunneling effect

14. Principles for Power Reduction • Prime choice: Reduce voltage! • Recent years have seen an acceleration in supply voltage reduction • Design at very low voltages still open question (0.6 … 0.9 V by 2010!) • Reduce switching activity • Reduce physical capacitance • Device Sizing

15. Factors affecting leakage power • Temperature • Sub-threshold current increases exponentially • Reduction in Vt • Increase in thermal voltage • BTBT increases due to band gap narrowing • Gate leakage is insensitive to temperature change

16. Factors affecting leakage power • Gate oxide thickness • Sub-threshold current decreases in long channel transistors and increases in short channel • BTBT is insensitive • Gate leakage increases as thickness reduces

17. Solutions • MTCMOS • Dual Vt • Dual Vt domino logic • Adaptive Body Bias • Transistor stacking

18. Metrics • Power Delay product • Energy Delay Product • Average energy per instruction x average inter instruction delay • Cunit_area • Capacitance per unit area

19. Conclusion • Power dissipation is unavoidable especially as technology scales down • Techniques must be devised to reduce power dissipation • Techniques must be devised to accurately estimate the power dissipation • Estimation and modeling of the sources of power dissipation for simulation purposes