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Electrical Engineering Department, Technion, Haifa, Israel. Automatic Hardware-Efficient SoC Integration by QoS Network on Chip. Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny. QNoC Research Group, Electrical Engineering Department
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Electrical Engineering Department, Technion, Haifa, Israel Automatic Hardware-Efficient SoC Integrationby QoS Network on Chip Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny QNoC Research Group, Electrical Engineering Department Technion – Israel Institute of Technology Haifa, Israel
Outline • Introduction: SoC Integration Challenge • NoC Concept and QNoC Architecture • SoC Automatic Integration by QNoC • Summary
The Integration Challenge: Growing Chip Density • Design complexity - High IP reuse • Scalable and Efficient, High Performance Interconnect • Integration Challenge 1998 Asic - 0.35 mm 2004 SoC – 90 nm Memory, I/O P
The Growing Gap: Computation vs. Communication From ITRS, 2001
Traditional SoC Nightmare • Variety of dedicated interfaces • Poor separation between computation and communication. • Design and Verification Complexity • Unpredictable performance
Solution – Network on Chip (NoC) • Scalability • Concurrency, effective spatial reuse of resources • Higher bandwidth • Higher levels of abstraction • Modularity – Productivity Improvement Easier SoC Integration!
NoC vs. “Off-Chip” Networks What is Different? • Routers on Planar Grid Topology • Short PTP Links between routers • Unique VLSI Cost Sensitivity: • Area-Routers and Links • Power
Example1: Replace modules Replace NoC vs. “Off-Chip Networks” • No legacy protocols to be compliant with … • No software simple and hardware efficient protocols • Different operating env. (no dynamic changes and failures) • Custom Network Design – You design what you need!
Adapt Links NoC vs. “Off-Chip Networks” Example2: Adapt Links Example3: Trim Unnecessary (ports, buffers, routers, links)
QNoC: QoS NoC Define Service Levels (SLs): • Signaling • Real-Time • Read/Write (RD/WR) • Block-Transfer • Different QoS for each SL
QNoC Architecture • Mesh Topology • Fixed shortest path routing (X-Y) • Simple Router (no tables, simple logic) • No deadlock scenario • Power efficient communication • Wormhole Routing • For reduced buffering
QNoC Wormhole Router Output Port Input Port
System Integration and Verification SoC development with QNoC System Architecture Definition
Integration Automation Tools QNoC Placement and Topology Generation • Analyzes System Modules and Traffic • Derives NoC Topology and Module Placement • Minimizes Spatial Traffic Density For Lower Area and Power
Integration Automation Tools QNoC Customization • Maze-Router – for efficient packet routing • Link Load Calculator – for capacity allocation • QNoC Network Simulator – for QoS assuring Simulated QoS Placed Modules Relative Link Load
Integration Automation Tools Automatic Hardware Generation • Use calculated QNoC parameters and QNoC VHDL templates library • Create Synthesizable VHDL description of QNoC • Including • Module wrappers • Synchronization and SER/DES circuitry • Routing logic and tables System Verification • QNoC verification models • For hardware and system simulations
Summary • SoC Integration Challenge • NoC Concept • QNoC Architecture • SoC Integration by QNoC • Automatic Integration Tools
More Info: www.ee.technion.ac.il/qnoc