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2. What is a SoC?. Technological advances allow electronic systems that earlier occupied one or more boards onto a single IC. The attending advantages are:Higher performanceLower Power consumptionSmaller volume and weightTypically, heterogeneous, containing a mix of:Digital logicMemories of di
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1. 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs
2. 2 What is a SoC? Technological advances allow electronic systems that earlier occupied one or more boards onto a single IC. The attending advantages are:
Higher performance
Lower Power consumption
Smaller volume and weight
Typically, heterogeneous, containing a mix of:
Digital logic
Memories of different formats and types
Analog circuits
Embedded cores
3. 3 What is a core? Large, reusable building blocks
Reuse speeds up design, brings in external expertise.
Typical core functions:
CPUs and DSPs
Serial interfaces
Modules for interconnect standards, e.g. PC, USB, IEEE 1394 (Firewire), and for graphics computation, e.g. MPEG and JPEG
Memories
Core Types:
Soft (RTL code)
Firm (netlist)
hard (layout)
4. 4 Core Providers vs. Core Users Cores have changed the nature of components used in system design:
In traditional system-on-board design provided components were ICs, designed, manufactured, and tested by the provider. Users could assume components to be fault-free and needed to test only interconnect between the components.
In SoC, components are cores (soft, firm, or hard) that are not yet manufactured or tested for defects.
5. 5 New Testing Issues in SoCs Core user responsible for manufacturing and testing the SoC
However, this is not possible without the assistance of core provider because core design is hidden for IP reasons.
Typically, core provider assists by delivering pre-defined tests with the core.
The problem that faced the SoC designers was how to apply these tests at the core boundaries.
IEEE 1500 developed to address the problem.
6. 6 Generic Test Access Architecture Architecture components
Source
Sink
TAMs
Wrapper
Source/sink can be external or internal to the chip.
7. IEEE 1500 History June 1997: P1500 Working Group started developing the standard and worked for 8 years.
2005: IEEE Std 1500-2005 approved and released.
Also approved in 2005 was IEEE Std 1450.6-2005, the Core Test Language CTL used to communicate information about core tests. 7
8. IEEE 1500: What is it? Provides a standardized infrastructure for modular testing of the digital portion (logic/memory) of SoCs.
Defines a hardware wrapper (with mandatory and optional features) that encapsulates embedded module under test and provides in the test modes:
Module isolation and environment isolation
Test control and test data access
Defines serial and parallel test-access mechanisms (TAMs) and an instruction set for testing cores, SoC interconnect, and circuitry.
Defines a standardized model for test information that must come with every IP Core (the information itself is described in IEEE 1450.6, Core Test Language (CTL)
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9. 9 IEEE 1500: Purpose Reduce test cost through improved automation, promote good design-for-test (DFT) technique, and improve test quality through improved access.
Scalable standard architecture for test reuse and integration for embedded cores and associated circuitry.
10. Wrapper Architecture Prefix W = Wrapper
WBR: Boundary Reg.
WBY: Bypass
WIR: Instruction Reg.
WPI/PO: Parallel I/O
(Optional)
WSI/SO: Serial I/O
Carries both wrapper instructions and test data
WSC: Serial Control (see next slide)
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11. WSC Signals WRCK (wrapper clock): Clock for WIR, WBR and WBY
WRSTN (wrapper reset): Asynch reset puts wrapper in normal functional mode
SelectWIR: Determines if WIR is used for instructions or test data
ShiftDR, CaptureDR, UpdateDR and (optional) TransferDR: Enables corresponding operation to the selected Wrapper register, in synch with WRCK 11
12. 12 Wrapper Instructions
13. 13 Timing: WIR shift, then WIR Update
14. 14 Wrapper Boundary Cells
15. 15 Wrapper Serial Bypass Example
16. 16 Wrapper External Test Mode
17. 17 Core Test Language (CTL) Purpose: Support all information the core provider needs to give for embedding the core in a SoC.
Requirement: Patterns, which contain bulk of the test data, are reusable without any modification.
18. 18 SoC Test Challenges Core Test
Providing DfT inside cores and test patterns to linked by SoC designer to chip-level test patterns sources and sinks that may be on-chip (BIST) or off-chip (ATE)
Core Test Access: Problems relate to deep embedding of cores and their large I/O pins compared to chip I/O pins. Sophisticated TAMs provide the solution.
SoC Level Test: How to integrate individual core tests and tests for interconnect? The solutions take the form of test scheduling strategies.
19. 19 Two Compliance Levels Unwrapped Cores: Bare core - no wrapper - but must have a CTL program for core test at the bare-core level, which can be used to design a 1500-wrapped core.
Wrapped Cores: IEEE 1500 wrapper + CTL program.
20. Example Core 20
21. 21 Example Core and Wrapper
22. Core with IEEE 1500 Compliant Wrapper 22
23. Normal and Serial Bypass Modes 23
24. Serial Internal and External Test Modes 24
25. Parallel Internal and External Test Modes 25
26. Starting References E. J. Marinissen et al., On IEEE P1500s Standard for Embedded Core Test, JETTA, Aug 2002.
IEEE Design & Test, Special Issue on usage experience with IEEE 1500, Jan/Feb 2009.
E. J. Marinissen and Y. Zorian, IEEE Std 1500 Enables Modular SoC Testing, a tutorial introduction in reference 2 above, pp. 8-16. 26
