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PD 32. MEMORIA. 32. DB. 30. AB. 8. CB. 32. CB. IACK. 6 MWR MRD Mbi i=1..4. AB. 8. DB. 32. 8. CLEAR. IACKout. Reg In. s. Q. r. Reg Out. s. Q. r. IRQ. s. SCO DEV 1. Q. r. 2. 4. s. Q. r. Interrupt. 2. IVN 1. Dev Sel. 2. IVN 2. Reg In. IVN 3. Bcar.
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PD 32 MEMORIA 32 DB 30 AB 8 CB 32 CB IACK 6 MWR MRD Mbi i=1..4 AB 8 DB 32 8 CLEAR IACKout Reg In s Q r Reg Out s Q r IRQ s SCO DEV 1 Q r 2 4 s Q r Interrupt 2 IVN 1 Dev Sel 2 IVN 2 Reg In IVN 3 Bcar Reg Out IVN 4 30 lsb 30 SCO DEV 2 2 CAR 1 I/O WR CAR 2 START 2 CAR 3 CAR 4 4 START 1 Reg In 4 START 2 Reg Out SELECT 4 WC 1 START 3 WC 2 SCO DEV 3 START 4 2 4 WC 3 DECR I/O WR WC 4 2 2 Dev Sel 32 Reg In 4 lsb Reg Out I/O FF 1 I/O FF 2 I/O WR SCO DEV 4 NEXT DATO 2 4 I/O FF 3 DATO SCRITTO I/O FF 4 MBG 2 DATO PRONTO 4 lsb MBR (esce da un Flip/Flop) SCO DMAC 4 DATO LETTO BURST 1 I/O WR BURST 2 2 DEV SEL BURST 3 BURST 4