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System Overview of the Phase 1 Pixel Upgrade

System Overview of the Phase 1 Pixel Upgrade. CMS Upgrade Workshop CERN 14. May 2009 R. Horisberger Paul Scherrer Institut. Pixel Upgrade Phase 1 (2014). BPIX 3 Layer  4 Layers FPIX 2x2 Disk  3x2 Disk CO2 cooling based Ultra Light Mechanics

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System Overview of the Phase 1 Pixel Upgrade

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  1. System Overview of the Phase 1 Pixel Upgrade CMS Upgrade Workshop CERN 14. May 2009 R. Horisberger Paul Scherrer Institut

  2. Pixel Upgrade Phase 1 (2014) • BPIX 3 Layer  4 Layers • FPIX 2x2 Disk  3x2 Disk • CO2 cooling based Ultra Light Mechanics • Shift material budget out of tracking eta - region • Modify PSI46 ROC for 160MHz digital readout & Increase depth of ROC buffers • Serialized binary optical readout at 320 MHz to modified px-FED (new piggy cards) • Rebuilt new AOH lasers  320MHz binary transmission • Same FEC’s , identical TTC & ROC programming • Use existing fibres & cables • Keep LV-power supply & push more current through cables

  3. DOH & AOH mother board + AOH’s Power board endflange prints Layer 3 & 1+2 20 BPIX supply tube FPIX service cylinder 10 0 80 100 20 40 60 Current Pixel System with Supply Tubes / Cylinders

  4. BPIX Cabling & flexible cooling pipes

  5. DOH & AOH mother board + AOH’s power board 20 Move DOH & AOH boards back by 50-60cm FPIX service cylinder 10 0 80 100 20 40 60 Shift Material out of tracking Volume  new BPIX modules with long pigtails (~1.2m) (  micro-twisted pairs)

  6. BPIX/FPIX Envelope Definition for 4 Layer Pixel System All barrel layers 4 module long  small eta hole of Dh ~ 0.08 at h=1.288 Various iterations forth and back by R.H. / Silvan Steuli / Kirk Arndt  no further changes since 2.12.2008 !

  7. R 144.6 mm FPIX Conceptual Layout 2014 FPIX 2x3 Disk Present FPIX 2x2 Disk R 161 mm R 58.7 mm R 39 mm • 72 outer & 44 inner radius modules • 1 module geometry • 116 modules per disk  1856 ROCs Total 6x1856 = 11’1136 ROC • 7 module geometries • 168 modules per disk Total 4x1080 = 4320 ROC

  8. BPIX Upgrade Phase 1 (2013)  1216 modules (1.6 x present BPIX)

  9. Each half shell has 10 cooling loops Each supply tube feeds 5 cooling loops Angle bend (~30) during insertion taken by carbon fibre hinge Inertion of BPIX – Supplytube System with new CO2 Cooling New axis of rotation (~3 degrees) during pixel insertion Carbon fiber hinge Stainless steel tubes diameter = 1.8mm wall thickness = 100μm

  10. Prototype Fabrication Layer 1 100 bar pressure tested Tubes, 50m wall thickness Weight Layer1 42g + 7g CO2

  11. Test of long CO2 cooling loop ( as in Layer 1) Cooling tubes are electrically isolated to the stainless steel facets Stainless steel facets used as heater resistors to simulate the power consumption of the sensor modules. Daisy chained connected (blue cable). Thermal isolation material. Top lid not shown.

  12. CMS Pixel Read Out System 320 MHz binary optical px-AOH 320 MHz binary 40MHz analog optical 40 MHz analog out A B px-FED I2C PLL Delay25 px-DOH crt, 40MHz fast I2C New Phase 1 System: 0-suppressed serial binary data readout at 320MHz, same data structure px-FEC I2C Current System: 0-suppressed analog coded data readout at 40MHz CCU trk-FEC

  13. Analog readout (40MHz) • serial (1 or 2 channels) • Double columns in ROC blocked until read out skip controlled by serial readout token: TBM-ROC1-…-16-TBM analog multiplexer and line-driver in TBM BPIX module 4 x 4 ROC  TBM  AOH  pxFED A - channel B - channel

  14. ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC A fibre analog summing amplifiers TBM B fibre analog summing amplifiers Current Pixel Module Readout ROC  TBM : 40 MHz analog readout TBM  pxFED : 40 MHz analog readout 40 MHz Layer 1& 2  2 Fibre A & B Layer 3  1 Fibre A

  15. Present analog coded data transfer of pixel system Pixel uses analog coded digital pixel readout Pixel address 5 x 3 bit Pulse height 1 x 8 bit  total 23 bits/ pixel hit in 6 clock cycles chip header 1 pixel hit 8 levels = 3bits c1 c2 r1 r2 r3 ph ub b 3rd • 160 Mbits/sec link speed resp. 1300 pJ/bit

  16. ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC ROC TBM New Serialized Binary Pixel Module Readout ROC  TBM : 160 MHz digital readout TBM  pxFED : 320 MHz digital readout 160 MHz analog summing amplifiers Layer 1 - 4  1 Fibre/module 320 MHz analog summing amplifiers

  17. 25ns time New serial binary data transfer of pixel system 40 MHz LHC Clock 1111 1111 XXXX 1010 1011 1001 1011 0001 1011 row/column address pulse height ROC header 12 bit long 1 pixel hit 150nsec long 24 bits with 160 MHz New ROC serial bit clock is 160MHz  4 bits / LHC clock cycle 160 MHz clock to be generated in each ROC by 40 MHz  160 MHz PLL circuit  See talk H-C. Kästli

  18. deserializer plug in card Changes for 160/320 MHz serial binary readout Changes Core of ROC chip unchanged but modified I/O periphery: 1) address DAC removed 2) 1 ADC for pulse height added 3) 40MHz 160MHz PLL added 4 x 4 ROC replace present ADC plug-in card with deserializer card Pixel ROC 26 dcol 160 pix/each New TBM purely digital chip no x-tra data buffering Multiplex 2 token passages 160 MHz PLL 1x ADC (8-bit) 160 MHz serial binary pxFED 320 MHz serial binary TBM-chip 160/ 320 MHz PLL

  19. Implications for the ROC • Core of chip untouched ! • Only changes to periphery Pixel cell • Remove DAC • Add PLL • 40 MHz 160 MHz • Add 160MHz bit serializer • Replace analog driver with • digital driver ADC PLL column periphery 40MHz

  20. HEPHY, Vienna M.Pernicka H. Steininger M. Friedl Pixel FED 3x 12 channels with 9 piggy-back ADC cards Replace ADC cards with new deserializer piggy-back cards

  21. Opto-Rx Measurements for Pixel Upgrade M.Friedl, M.Pernicka HEPHY Vienna

  22. What? Why? How? • Digital optical 320 Mb/s transmission is intended for pixel phase 1 upgrade • Recycling of existing optical links possible? • Sender side appears OK • Most severe bandwidth limitation in12-way receiver (ARx12) ~100 MHz • Comparative test of digital transmission at 320 Mb/s between existing ARx12and Zarlink engineering sample • Each mounted on test board(clean environment) • ARx12 with external fast, self-biased,LVDS-output comparators (ADCMP604) ARx12 Comp. Zarlink

  23. Sender / Receiver Setup AOH test setup Agilent 8110A pulse/pattern generator Receiver boards Tektronix DSA70804 Scope AOH (TOB type)

  24. Test A – Unbalanced Periodal Signals Ton Tperiod • 40 MHz with variable duty cycle (Ton/Tperiod) • Considerable distortions up to misinterpretation due to threshold imbalance • Bad result. However: This is a very unrealistic situation… Example: 25% duty cycle represents repetitive unbalanced 1100 0000 code Receiver

  25. Test B – Balanced PRBS @ 320Mb/s with Sequence of 0s or 1s • 15000 words of programmable pattern filled with PRBS14 (=balanced) • Programming 1s (or 0s) from the beginning of the pattern until remaining PRBS bits become corrupted • Amazing result: • Zarlink tolerates ~700 consecutive 1s (or 0s) without effect on subsequent pattern • With more than ~700 same symbols, subsequent single bits deteriorate or vanish completely (symmetric behavior) • ARx12 even tolerates ~3000 consecutive 1s • Perfectly suitable for pixel system, where even 20 consecutive 1s or 0s are extremely unlikely

  26. Test C – Eye Diagram @ 320Mb/s (1) • Optical Head (analog) • Limited rise time (mostly due to pattern generator) • Stable timing • Solid eye opening

  27. Test C – Eye Diagram @ 320Mb/s (2) • Zarlink (digital) • Perfectly fine • High bandwidth(Zarlink can do 1.6Gb/s)

  28. Test C – Eye Diagram @ 320Mb/s (3) • ARx12+comparator (digital) • Narrow opening with best settings of pulse generator (amplitude),AOH (offset) and Rx12(offset) • Unusable with non-optimal settings(where Zarlink still works perfectly well)

  29. Test Conclusions • ARx12 performance is marginal – even on a lab test bench in a noise-free environment • Needs careful tuning of parameters in order to work • Hence we don’t recommend its use in a production system • Zarlink works very well – but is not a commercial product • Normally 850nm, this engineering sample has 1310nm photodiode • Francois is in contact with manufacturer to see if we can get 200 pcs. of 1310nm wavelength version • H. Steininger has proposal to recover the phase for the 320MHz digital data stream at deserializer board on pxFED

  30. Modification of Pixel-FED (1) • Keep single slot size • Keep VME base board New daughter board(instead of 3 ADC cards)including Zarlink receiver • Don’t need to remove current ARx12  allowseasy swapping betweenold and new systems • Need new front panelin any case

  31. Modification of Pixel-FED (2) Front panel ARx12 Old ADC card OLD ARx12 New daughter board NEW VME board Zarlink (mountedon daughter board) Need higher connectors than nowAvailable from different vendor (samples ordered for compatibility tests)

  32. Situation at present 32 cables → layers 1+2 (192 ROCs) 32 cables → layer 3 (128 to 192 ROCs) New Proposed Layout 32 cables → layers 1+4 (320 ROCs) 32 cables → layers 2+3 (256 to 320 ROCs) Power for BPix Phase-1 Number of Power cables won’t change! (calculated for luminosity = 1034) W. Bertl PSI

  33. Bpix Operation Parameters BPix 2008 | BPix 2013 Luminosity 1 x 10341 x 1034 2 x 1034 5 x 1034 Power Dissipation 1612 W | 2598 2919 3883 W Analog Voltage 1.7 V | 1.7 V Digital Voltage 2.5 V | 2.5 V Analog Current 293 A | 494 494 494 A Digital Current 446 A | 703 832 1217 A W. Bertl PSI

  34. CAEN A4603 Power Supplies Present Limitations Voltage: Set Point (max.) Full Range Output Analog 2.3 V 5.7 V Digital 3.0 V 6.9 V Current: Analog 6 A ~ 6 A Digital 15 A ~ 15 A Power (single PSU): each line individually both lines loaded Analog 33 W 28 W Digital 99 W 88 W 116 W W. Bertl PSI

  35. A4603 Requirements Required (max.)* Possible at present (1034 luminosity) Full Voltage: Analog 7.5 V 5.7 V Digital 7.5 V 6.9 V Current: Analog 9 A 6 A Digital 13 A 14.5 A Power: Analog < 68 W 28 W Digital < 98 W 88 W 166 W !!! 116 W Total Power needed:7.1kW Power loss in cables:4.5 kW 8 modules in a crate exceed 48V supply capacity by 30% ! * < 10% contingency included W. Bertl PSI

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