Combinational Redundancy Identification

1. Combinational Redundancy Identification Student: Yi-Yuan Huang Advisor: Chun-Yao Wang 1

2. Outline • Introduction • Problem Formulation • Initial Method • Dilemma • How To Solve • Previous work • Terminology • Advanced Techniques • Check up criterion • Quit line 2

3. Outline • Flow • Conclusion • Experiment Result • Future work 3

4. Introduction • Stuck-at fault model • The test generation is to generate the corresponding test vectors for all signals’ stuck-at fault b is connected to ground or Vdd mistakenly 4

5. Cont’ • For combinational circuits, an undetectable fault is corresponding to a redundant wire • Redundancy can cause • Lower fault coverage • Increase circuit size • Increase dynamic power consumption • Increase propagation delay 5

6. Problem Formulation • Given a combinational circuits composed of AND, OR, and NOT gate • Try to provide an efficient irredundancy identification tool to filter the irredundant wire 6

7. Initial Method • Parallel patterns single fault simulation (PPSFP) • Take advantage of word size of the host machine to simultaneously fault simulate with multiple patterns • Parallel computing to speed up • Critical path tracing • Sensitized path backtracing • Find faults detected by a test w/o simulating all faults one by one (exact for tree structure) • PPSFP + Critical path tracing 7

8. Dilemma • Self-masking • A fault can not be detected, but we say it can be detected 1 1 0 a b1 1 0 1 1 b d b2 0 1 0 1 1 c 8

9. Cont’ • Multiple-path sensitization • A fault can be detected, but we say it can not be detected 1 0 1 a 1 0 b1 1 0 b b2 1 0 d 1 c 9

10. Cont’ • Fault grading • Trading some loss of accuracy in the results for a significant reduction in computational cost 10

11. Cont’ • Redundancy identification can not endure self-masking Total faults Identified irredundant faults ATPG-based method Not sure Candidate redundancy 11

12. How To Solve • Previous work • [1] KURT J. ANTREICH and MICHAEL H. SCHULZ, “Accelerated Fault Simulation and Fault Grading in Combinational Circuits,” IEEE TCAD, 1987 [2] Ohyoung Y. Song and P. R. Menon, “Parallel Pattern Fault Simulation Based on Stem Faults in Combinational Circuits,” IEEE ITC, 1990 [3] Ohyoung Y. Song and P. R. Menon, “Accelerated of Trace-Based Fault Simulation of Combinational Circuits,” IEEE TCAD, 1993 12

13. Terminology • Stem • For a signal, the number of fanout is more than one • Fanout Free Region(FFR) • The circuit is tree structure, that is , the critical path tracing method can correctly implement • Surrogate line • The output of FFR 13

14. Cont’ Ex: An FFR is represented by the line at its output, which is called the surrogate line of the FFR 14

15. Cont’ • Criticality • If test vector t detects the line L s-a-0 fault, L is said to be 1-critical in t, and vice versa • Stem-critical • A line L is 1-stem-critical in t, if t propagates L s-a-0 fault to its surrogate line, vice versa • Because FFR is tree structure, so critical path tracing will work 15

16. Cont’ • Chain rule • A line L is 1-critical in t, if the line L is 1-stem-critical and its stem is critical in the test t FFR Fanout cone 16

17. Cont’ • Stem analysis • Invert its value (fault injection), then forward simulate to see if its fault effect can be observed in POs 1 0 1 a 1 0 b1 1 0 b b2 1 0 d 1 c 17

18. Advanced Techniques • Check-up criterion • If any fault in the FFR is stem critical and undetected, checking the corresponding stem’s criticality. {1,2} 0110 {0~2} 0110 {1,2} 1111 {0~2} 1000 {1,2} {3} 1100 {0~3} 1000 {3} 1000 {0,3} {3} Checkup:{1,2,3} 18

19. Cont’ • Quit-line • A line p in an FFR is a 0(1)-quit line for a test set t, if t detects all detectable faults in the FFR that their fault effect propagation cause p to assume value 1(0) 19

20. Cont’ • FFR dropping • A FFR with no undetected fault, so we need not check the FFR in the following iteration 20

21. Cont’ • Stem graph a a e e b f d d b c f c 21

22. Cont’ Join stem 3 4 1 2 d 7 0 3 1 8 3 4 c h 2 1 5 2 b e 4 1 a 6 3 7 4 j g 7 6 9 3 3 4 f i 3 6 10 1 6 22

23. Cont’ Fanout cone Fanout cone 23

24. Flow • Perform parallel patterns logic simulation • Backtracing stops at FFR inputs or quit lines, whichever is encountered first • During the second backtracing, new quit line are identified in addition to gathering detection information 24

25. Cont’ Read circuit Checkup is not ZERO no yes Stem analysis Iteration limit or all fault detected finish yes no no Stem is critical? Parallel pattern Logic simulation no yes Irredundant identification in FFR Any active FFR yes Select one, evaluate stem-criticality 25

26. Conclusion • We make use of this algorithm as an engine to find the irredundant wires efficiently and exactly 26

27. Experiment Result • Iteration: 10; Frame size 32768(215) :rot, term1 • Frame size 65536(216) :C3540, C5315 • Frame size 262144(218) :count, pair • Frame size 524288(219) : t481 • Frame size 4194304(222) :too_large; Frame size 8192(213) :others 27

28. Cont’ 28

29. Future Work • Find the relation between the frame and testability 29