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ECT 358. Lecture 10 Counters. Success in marriage is more than finding the right person. It’s becoming the right person. But thou, O man of God, flee all things; and follow after righteousness, godliness, faith, love, patience, meekness. 1 Timothy 6:11. Counter Types . Up/Down
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ECT 358 Lecture 10 Counters
Success in marriage is more than finding the right person. It’s becoming the right person. But thou, O man of God, flee all things; and follow after righteousness, godliness, faith, love, patience, meekness. 1 Timothy 6:11
Counter Types • Up/Down • Ring Counter • Circular shift register with only one bit set • BCD (Binary Coded Decimal) • Counts from 0000 to 1001. Next count after 1001 is 0000 • Modulo N counter • Counts from zero to N-1. (e.g. BCD is modulo 10 counter) • Johnson Counter
Binary Up/Down Counter • Inputs • - Inc • - Dec • - Data • - Clock • - load • Outputs • - Count • Behavior • If inc is true, count = count +1 on clock edge • If dec is true, count = count –1 on clock edge • If ld is true, count = data on clock edge • If inc and dec are true, count = count • Load takes priority over count
Binary Up/Down Counter data load inc dec clock count
Binary Up/Down Counter //up_down_counter.v //parameterized binary up/down counter module up_down_counter(COUNT,clk,inc,dec,load,DATA); parameter width = 4; output [width-1:0] COUNT; input [width-1:0] DATA; input clk, inc,dec,load; reg [width-1:0]COUNT; always @(posedge clk) if (load) COUNT <= DATA; else if (inc && dec) COUNT <= COUNT; else if (inc) COUNT <= COUNT +1; else if (dec) COUNT <= COUNT -1; else COUNT <= COUNT; endmodule
Modulo N Counter //mod_count.v //a modulo N counter example module mod_count(count, N, clk); parameter width=16; output [width-1:0]count; input [width-1:0]N; //the actual width of N is log2 (N) input clk; reg [width-1:0]count; always @(posedge clk) if (count < N-1) count <= count +1; else if (count == N-1) count <= 0; endmodule
Program Counter //reg_counter.v //A register counter used for the program counter module reg_counter(X, ld, clk, inc,Y); parameter width=8, increment=1; input [width-1:0] X; input ld, clk, inc; output [width-1:0] Y; reg [width-1:0] Y; always @(posedge clk) if (ld) Y[width-1:0] <= X[width-1:0]; else if (inc && !ld) Y[width-1:0] <= Y[width-1:0]+ increment; endmodule