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ECT 358

ECT 358. Lecture 3a CPLD’s. Luck: a loser’s excuse for a winner’s position. The soul of the sluggard desireth, and hath nothing: but the soul of the diligent shall be made fat. Proverbs 13:4. Complex Programmable Logic Device (CPLD). Large structures of combinational logic

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ECT 358

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  1. ECT 358 Lecture 3a CPLD’s

  2. Luck: a loser’s excuse for a winner’s position. The soul of the sluggard desireth, and hath nothing: but the soul of the diligent shall be made fat. Proverbs 13:4

  3. Complex Programmable Logic Device (CPLD) • Large structures of combinational logic • Programmable on chip interconnect fabric • Made of PLD blocks • Wide fan-in AND gates • PAL like internal structure • Internal outputs routed to other inputs • Erasable PLD (EPLD) • SRAM/transmission gates • EPROM • Antifuses (low resistance links) • Sharable Expanders

  4. Complex Programmable Logic Device (CPLD)

  5. Complex Programmable Logic Device (CPLD) • Up to 1024 functions • Large number of inputs • Large Area • 100% connectivity between PLD cells

  6. Altera 7000 Architecture (CPLD) • Floating gate EEPROM configuration memory for routing • Logic Array Blocks (LAB’s) • Same architecture • Programmable Interconnection Array • Global bus between I/O and LAB’s • Programmable I/O blocks • Connect clocks to all macrocells

  7. Altera 7000 Architecture (CPLD)

  8. Altera 7000 Macrocell Architecture • Programmable AND plane • Product Term select matrix for OR gate • Programmable Flip-flop • Mini-PAL architecture • Flip flop gated by clock or product term • Expander Signals

  9. Altera 7000 Macrocell Architecture

  10. Altera 7000 Shareable Expander • Enable shared product terms • Increase number of literals for expressions • Inverted and sent to other macrocells • Shared product resources

  11. Altera 7000 Shareable Expander

  12. Altera 7000 Parallel Expander • Share up to 15 product terms with neighboring macrocells • Chain beginning and end

  13. Altera 7000 Parallel Expander

  14. Altera 7000 I/O and Timing • Dedicated input or output or bidirectional • Timing is predictable • All inputs can go to any cell • Channel vs fabric tradeoffs (routing delays) • Synthesis tool optimizes for resources • In system programmable

  15. Xilinx XC9500 Architecture (CPLD) • Flash based in system programmable • PAL structure • FastCONNECT switch matrix • I/O blocks buffer inputs and outputs • Programmable slew rate • 90 product terms / macrocell

  16. Xilinx XC9500 Architecture (CPLD)

  17. Xilinx XC9500 Macrocell Architecture • 288 Macrocells • 6400 gates • 288 registers • 5 ns propagation delay (fixed) • 250 MHz • Predictable performance independent of the internal placement and routing of design

  18. Xilinx XC9500 Macrocell Architecture

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