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Understanding ADC Specifications

Understanding ADC Specifications. September 2005. Ideal transfer function for a 3-bit A/D. Definition of Terms. Transition point is where the output code changes from one code to an adjacent code with respect to an analogue input voltage V REF = Full-Scale (FS) + 1LSB Voltage

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Understanding ADC Specifications

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  1. Understanding ADC Specifications September 2005

  2. Ideal transfer function for a 3-bit A/D Definition of Terms Transition point is where the output code changes from one code to an adjacent code with respect to an analogue input voltage VREF = Full-Scale (FS) + 1LSB Voltage Ideal code Width = 1LSB 1 LSB = VREF / 2n ie: VREF = 4.096V, for a 12-bit ADC LSB size = 4.096/212 = 1mV 111 110 Transition Points Digital Output Code 101 100 011 code width 010 001 000 0 1/4 FS 1/2 FS 3/4 FS FS Analogue Input Voltage

  3. ADC Specifications: Resolution • For an ADC, Resolution is simply a measure of how many segments the input analogue range can be divided into. • Resolution IS NOT THE SAME AS ACCURACY! • You could have a 16-bit ADC that is less accurate than an 8-bit ADC • Why? Monotonicity, A/D converter noise, etc

  4. ADC Specs: Quantisation Error The difference between the actual input voltage and the digital code representation of the input voltage. Even in the case of a perfect ADC, quantisation error will be ± 1/2 LSB. Increasing bits reduces the error 111 110 Digital Output Code 101 100 011 010 001 000 0 1/4 FS 1/2 FS 3/4 FS FS Analogue Input Voltage

  5. Sampling and Quantisation Quantisation Error 1111 1110 1101 ADC Output 1100 1011 1010 OUTPUT DIGITAL WORD 1001 1000 0111 TIME 2 3 4 5 6 7 8 9 10 11 12 13 0110 0101 Input Sinewave 0100 0011 0010 0001 0000 4-bit (16 level) ADC sampling a sinewave input, time domain

  6. 0 1/4 FS 1/2 FS 3/4 FS FS ADC Specs: Offset Error Offset Error is the difference between the first transition point and the ideal first transition point. (Measured in LSBs) Digital Code Out = A + Vin where A is the analogue offset error Offset Errors can be corrected in Firmware Correction for offset error can be made by adding (or subtracting) the correction from each code. 111 110 Ideal transfer function 101 Digital Output Code 100 011 Actual transfer function 010 001 Offset Error 000 Analog Input Voltage

  7. ADC Specs: Gain Error (full scale error) Full scale range is the difference between the first and last code transition points. The ideal full scale range minus the actual full scale range equals Gain Error. (Measured in LSBs) Digital Code = B VIN where B is the gain error Gain Errors can be corrected in firmware Corrections for gain error can be made by multiplying each code by the ratio of ideal to actual full scale range. 111 110 Actual transfer function 101 Digital Output Code 100 011 Ideal transfer function 010 001 000 Ideal full scale range Actual full scale range

  8. ADC Specs: A/D Converter with Offset and Gain Error 0 1/4 FS 1/2 FS 3/4 FS FS 111 With most ADCs, you will have to deal with both Gain and offset Errors! Digital Code = A + B VIN where A is the Offset Error and B is the Gain Error 110 Actual transfer function 101 Digital Output Code 100 011 Ideal transfer function 010 001 000

  9. ADC Specs: Differential Nonlinearity (DNL) 111 DNL is a measure of variations in code widths from the ideal code width. A DNL of ±½ LSB implies that: ½ LSB < all code widths < 1½LSB A missing code means DNL = -1 LSB 110 Actual transfer function 101 Digital Output Code 100 Ideal transfer function 011 010 Wide code, >1 LSB 001 000 Narrow code, <1 LSB

  10. DNL Plot for 12bit ADC 4095 0 This DNL plot shows the variation of code widths for each code for a 12 bit ADC

  11. ADC Specs: Missing Codes If the DNL spec goes beyond -1LSB, then missing codes will appear. The term ‘No Missing Codes’ means that no digital output codes are skipped as the analog input is swept from zero to full scale. Most ADCs today will include the specification ‘No missing codes’ 111 The 100 Code is ‘Missing’ 110 101 Digital Output Code 100 011 010 001 000 0 1/4 FS 1/2 FS 3/4 FS Analogue Input Voltage

  12. ADC Specs: Monotinicity If the output code of an ADC is guaranteed to output increasing codes as long as the input signal is increasing, it is called Monotonic If at some point in the transfer function the digital output code decreases as the analog input increases, then it is non-monotonic. Almost all ADCs on the market today are guaranteed monotonic 111 Non-monotonicity 110 101 Digital Output Code 100 011 010 001 000 0 1/4 FS 1/2 FS 3/4 FS Analog Input Voltage

  13. ADC Specs: Integral Nonlinearity (INL) INL is the maximum deviation between an actual code transition point and its corresponding ideal transition point. Measured in LSBs, and calculated after offset and gain error have been compensated for. This is a measure of the transfer function’s deviation from linearity. A positive INL indicates transition(s) occurring later than ideal. Negative INL means transition(s) earlier than ideal Actual transfer function INL < 0 111 110 101 Digital Output Code 100 Ideal transfer function 011 010 001 000 INL < 0

  14. ADC Specs: Integral Nonlinearity (INL) This diagram shows an INL error greater than zero whereas the previous diagram showed INL errors of less than zero. As you may have guessed, INL and DNL are very closely related; if you have one you also always have the other INL > 0 Ideal transfer function 111 110 101 Digital Output Code 100 Actual transfer function 011 010 001 000 INL > 0

  15. INL Plot for a (poor, non Silabs) 12bit ADC 4095 0 This INL plot shows the variation of code transition points for each code for a 12 bit ADC

  16. AC Specs But First, a quick look at FFTs……

  17. 0 -20 -40 -60 -80 -100 -120 Fast Fourier Transforms (FFT) Input Signal Headroom 4096 points, fin = 10.2kHz, -0.5dB Number of points taken Input Signal Frequency Input Signal Amplitude (dB) 1/2 of Sampling Rate 50 10 20 30 40 Frequency (Hz)

  18. 0 4096 points, fin = 10.2kHz, -0.5dB -20 -40 -60 Amplitude (dB) -80 -100 -120 50 10 20 30 40 Frequency (Hz) Fast Fourier Transforms (FFT) Fundamental or Primary Frequency (The input signal) Harmonic or Secondary Frequencies (Distortion caused by the part Average Noise Floor

  19. ADC Specs: Total Harmonic Distortion (THD) • A frequency domain spec evaluated using an input sinewave and FFT analysis • Calculated as the ratio of the RMS sum of the number of harmonics (usually the first 5) to the RMS value of the input. It is always specified at a particular frequency and is measured in dB. • In layman’s terms, it is a measure of the amount of signal energy distributed in harmonics vs amount in primary • It is caused by A/D converter nonlinearities, which generate harmonics of the input signal which to appear in the output • Typical values are -78dB to -85dB.

  20. 0 0 -20 -20 -40 -40 -60 -60 -80 -80 -100 -100 -120 -120 THD(-dB) = 20LOG  (V2)2 + (V3)2 + … + (Vn)2 V1 THD Plot V1 (Fundamental) V2 V4 V3 V5 Amplitude (dB) Amplitude (dB) 50 50 10 20 30 40 10 20 30 40 Frequency (Hz) Frequency (Hz) Bad THD Good THD

  21. ADC Specs: Signal to Noise Ratio (SNR) • SNR is a frequency domain spec measured using a sinewave input and FFT analysis • It is the ratio of RMS signal amplitude to the RMS output noise for a specific input frequency and amplitude,excluding harmonic noise • In laymans terms, it’s a measure of how much noise is present with respect to the actual signal • It is expressed in dB • Ideal SNR is equal to (6.02n + 1.76 dB) where “n” is the number of bits • For 12-bit A/D, ideal SNR = 74dB

  22. ADC Specs: Signal to Noise and Distortion Ratio (SINAD) • SINAD is a frequency domain spec measured using a sinewave input and FFT analysis • It is the ratio of RMS signal amplitude to the RMS sum of the noise and distortion products for a specific input frequency and amplitude • In laymans terms, it’s a measure of noise generated by the part itself • It is expressed in dB

  23. Effective Number of Bits vs Noise-Free Bits • Assuming that system noise is Gaussian, histogram will approximate a Normal Distribution

  24. Noise-Free Resolution • “Effective Noise” is the specification that is used for dynamic signals • “Noise-Free Resolution” is the specification that is used for DC signals involving a display

  25. Example F350 calculation • Out of 1024 samples: • Min code = -33 • Max code = 32 • Average code = -0.5 • Variance = 123 • 1 sigma = sqrt Variance = sqrt (123) = 11 LSBs • RMS Noise = +/- 11 LSBs • Effective Bits = Log2(223/1 sigma) = 19.5 bits • Noise-Free bits = Log2(2^23/6.6*sigma) = 17 bits • 2^17 is 131,072, which equates to 5 ½ digits on the scale display

  26. ADC Specs: Effective Number of Bits (ENOB) • ENOB is a measurement of the resolution of the ADC and is directly related to Signal to Noise+Distortion (SINAD) • ENOB = [SINAD - 1.76]/6.02 • For ideal SNR (74dB) and no distortion, ENOB = [74-1.76]/6.02 = 12 bits!

  27. ADC Specs: Spurious Free Dynamic Range (SFDR) • SFDR is a frequency domain measurement that is evaluated using a sine wave input and FFT analysis • The SFDR is always given at a particular frequency • SFDR is the difference of Fundamental minus highest spur in dB. • In laymans terms, it’s a measure of the size of the biggest spike compared to the next biggest spike. In a perfect world, there would be only one big spike • The larger the number the better. SFDR specs range from 80 - 90 dB.

  28. 0 4096 points, fin = 10.2kHz, -0.5dB -20 -40 -60 Amplitude (dB) -80 -100 -120 50 10 20 30 40 Frequency (Hz) SFDR Plot Spurious Free Dynamic Range (SFDR) is the difference between primary and next highest spur SFDR

  29. ADC Specifications: Sample Time and Conversion Time • Every A/D conversion is made up of a sample or tracking period and a conversion period • The terms ‘track and hold’ and ‘sample and hold’ are sometimes interchanged, although most serial ADCs are ‘track and hold’ devices • The period of time when the input signal is sampled or tracked is the Sample Time. • Can be measured in time or number of clock cycles • Conversion Time is the time required to convert the sampled input signal to a digital word. • Can also be measured in time or number of clock cycles

  30. ADC Specifications: Throughput Rate • Throughput rate is the number of times you can do a sample + conversion in a period of time • Usually specified in ksps or Msps • Example: A fictitious SAR ADC with sample time of 2 clock cycles and 13 clocks required for a 12 bit word. (Fclk=1Mhz) 15 clocks * 1uS = 15us CS time = 600ns Period = 15us + 600ns = 15.6us ft = 1/15.6uS = 64 ksps

  31. www.silabs.com

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