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ALTERA APEX20K

ALTERA APEX20K. multicore strktura LUT logika, PT (product term) logika, EA logika napájení 1,8V a 2,5V I/O podpora 1,8V, 2,5V, 3,3V (DDR) a 5V podpora I/O standarů LVPECL, PCI-X, AGP, CTT, SSTL-3, SSTL-2, GTL+ a HSTL první třídy. Popis struktury. první PLD se strukturou Multi-Core

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ALTERA APEX20K

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  1. ALTERAAPEX20K • multicore strktura • LUT logika, PT(product term) logika, EA logika • napájení 1,8V a 2,5V • I/O podpora 1,8V, 2,5V, 3,3V(DDR) a 5V • podpora I/O standarů LVPECL, PCI-X, AGP, CTT, SSTL-3, SSTL-2, GTL+ a HSTL první třídy

  2. Popis struktury • první PLD se strukturou Multi-Core • členění do MegaLAB • spojení LUT, ProductTerm a paměťové struktury • Fast Track Interconnect • Clock Management cicuit • IOE

  3. Blokový diagram architektury

  4. MegaLAB Structure • každý Mega LAB obsahuje podle typu APEX20K 10,16 nebo 24 LAB

  5. Struktura LAB

  6. Kontrolní signály LAB

  7. Bloková struktura LE

  8. Fast Tack Interconnect struktura

  9. FastTrack Connection to Local Interconnect

  10. Driving the FastTrack Interconnect

  11. FastRow Interconnect

  12. Product-Term Logic in ESB

  13. Macrocell

  14. Parallel Expanders

  15. Embedded System Block ESB může implementovat různe typy paměťových bloků, dual-port RAM, ROM, FIFO a CAM(content addresable memory)blocks.

  16. Implementace ESB Dual-Port RAM CAM Block Diagram

  17. Read/Write Clock Mode

  18. Single-Port Mode

  19. Bidirectional I/O Registers

  20. I/O Banks

  21. I/O podpora

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