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MAVEN SWIA Electrical Pre-CDR Peer Review May 11, 2011

MAVEN SWIA Electrical Pre-CDR Peer Review May 11, 2011. E. Taylor Space Science Laboratory University of California - Berkeley. SWIA Electrical Team. Jasper Halekas (Instrument Lead) Ellen Taylor (Digital Electronics, Preamp Board, Anode Board) Dorothy Gordon (FPGA)

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MAVEN SWIA Electrical Pre-CDR Peer Review May 11, 2011

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  1. MAVEN SWIA Electrical Pre-CDR Peer Review May 11, 2011 E. Taylor Space Science Laboratory University of California - Berkeley

  2. SWIA Electrical Team • Jasper Halekas (Instrument Lead) • Ellen Taylor (Digital Electronics, Preamp Board, Anode Board) • Dorothy Gordon (FPGA) • Peter Berg (MCPHV Power Supply) • Selda Heavner (LVPS Power Supply Board) • Chris Tiu (Sweep HV Power Supply Board) • Peter Harvey (FSW [PFDPU]) • Dave Curtis (System Interfaces) • Tim Quinn (GSE) • Jorg Fischer (QA) • AnLoc Le (Parts Lead)

  3. Overview Block Diagram For each board (Digital, Pre-amp, Anode): Functional and Interface Requirements EM Verification/Status Changes since PDR Changes for Flight Note: HVPS/LVPS boards and FPGAs are covered in separate peer reviews. EM Integrated Electronics Test Results Parts Stress Analysis, Parts Status and Issues Review of Responses to PDR Actions/Recommendations

  4. Electrical Requirements and Interfaces REQUIREMENTS and SPECIFICATIONS MAVEN-PF-SWIA-001i SWIA Instrument Specification Functional and Performance Requirements Resource Allocations (board size, power budget) Environmental Requirements (thermal, vibration, radiation) MAVEN-PF-QA-002 UCB Mission Assurance Implementation Plan Parts Level, Burn-In, Derating MAVEN-PF-SYS-003 Power Converter Requirements Power voltages, current, ripple, transients MAVEN-PF-SWIA-012 FPGA Specification PFDPU CLK/TLM/CMD Interface HV Enable (RAW and MCP) and DAC Control (Sweep and Fixed) Pre-amp Input, Test Pulser Output Housekeeping and Memory (external SRAM) I/F INTERFACES (electrical only) MAVEN-PF-SYS-004 PFIDPU ICD PFDPU Serial I/F and power description MAVEN-PF-SYS-016 Pinouts Connector Description and Pin-outs MAV-RQ-09-0015 Particle and Fields to Spacecraft ICD Heater, Thermistor and Cover Actuator Interface

  5. SWIA Electrical Block Diagram

  6. SWIA Interconnect (Requirements) • Modular design for easy board-to-board assembly/disassembly (SWIA-017) • Connectors organized to minimize signal paths across and between boards (SWIA-024, -027) • HV routed safely from lower boards to deflectors and MCP through coax cables (SWIA-019) • Airborn WTAX stackable board-to-board connectors used when possible (SWIA-025) • Signal connectors between Anode-Preamp are Hypertronics KA-17 (SWIA-025) • Survival heaters and thermistors are redundantly controlled by the spacecraft (SWIA-010, -011), routed through connector and winchesters • Wiring to deflectors, actuator signals, etc. routes along housing on the anti-sunward side (+X), opposite the solar wind direction (SWIA-122, -123) TO PFIDPU

  7. SWIA Interconnect Changes since PDR PDR Revision (MAVEN-PF-SWI-SCH-005 rev 4) • Only very minor changes since PDR • HVPS Enable Plug moved from Digital Board to LVPS Board (easier mechanical access) • Attenuator signal comes into separate connector (SWI-J4) on the SWIA “dog-house” instead of being routed through Digital Board connector TO PFIDPU

  8. SWIA Interconnect EM Verification • Bare boards have been fully integrated and fit-checked in mechanical chassis • Basic stack-up assembly/disassembly verified • Minor issue with digital board-to-shield clearance. 2 parts on the bottom of board do not meet minimum dynamic clearance requirements. May require custom stand-off between board and shield. • Next step is to integrate loaded boards, check grounding scheme and noise environment (part of SWIA calibration)

  9. Anode Board Design (Requirements) Anode board routes signals from and HV to MCPs Consists of 10 x 4.5 and 14 x 22.5 degree discrete charge collection anodes centered around anti-sunward direction (SWIA-501) Metallization is directly on the board, with window between spacers exposing the anode pads to the MCP output face (SWIA-504) Mounts on a circular board with same outer diameter as E-box (SWIA-503) Signal routed through a surge resistor (51 ohms) to provide a DC path for anode current (SWIA-507) Drain resistor (1 Mohm) bleeds off charge and prevent discharge (SWIA-507) Two diodes provide a bipolar voltage clamp to suppress voltage spikes (SWIA-508) Signal connections have short path length to reduce capacitance, and are routed to avoid cross-talk and noise (SWIA-511) Board has internal ground plane shielding anodes from each other (SWIA-512) Large Anode Pad Small Anode Pads MCP Contact

  10. SWIA Anode Board Schematics PDR Slide Removed HV Capacitor (adequate keep-out zone difficult to maintain) Changed from custom HV capacitor rated at 3kV to standard 200V Ground Return Resistor Sets MCP Output Voltage 24 anodes split 12 to each connector 10 small plus 2 large anodes 12 remaining large anodes

  11. SWIA Anode Schematic Details PDR Slide Drain resistor provides DC current path Surge limit resistor Clamp diodes suppress voltage spikes

  12. Anode Board Design EM Verification Anode board fabricated, tested, integrated with SWIA EM MCPs and currently being used for MCP calibration No change to layout for flight except removing HV capacitor (EM testing is being conducted without capacitor on board)

  13. Digital Board Design (Requirements) Command/Data Interface to PFDPU (SWIA-912) Accumulate counts from each of the 24 anodes (SWIA-909) Bin data and generate data products for transfer to PFDPU (SWIA-907) Enable HVPS and control MCP high voltage (SWIA-916) Control voltage sweeps for analyzer inner hemisphere and deflectors (SWIA-902) Provide programmable threshold for anode pulse amplifiers (SWIA-911) SRAM for storing lookup tables and accumulators (SWIA-918) Generate test pulses (SWIA-908) Control ADC and MUX to read instrument housekeeping monitors (SWIA-910) Note: Digital board does not control heaters (S/C), cover actuators (S/C), or attenuators (PFDPU)

  14. SWIA Digital Board Interfaces FPGA Interface SWIA-012B FPGA Specification Power on Reset PFIDPU CLK/TLM/CMD HV Enable (RAW and MCP) DAC control (Sweep and Fixed) Test Pulser Output, Anode Input Housekeeping I/F Memory I/F (external SRAM) PFDPU Interface SYS-004B PFDPU ICD, Serial I/F SYS-013E Harness, J2 Pin-out LVPS Board Interface SYS-003C Power Converter Req. HVPS Board Interface RAW, SWEEP, DEF1/2 power, control and housekeeping Pre-amp/MCP Board Interface MCP power/control/hsk, test pulser, anode pulses

  15. SWIA Digital Schematics (FPGA) Test Pulse PDR Slide DAC I/F HV Enable HSK I/F Decoupling Caps 128K x 8 SRAM Pre-amp Inputs Test and Spares PFDPU I/F Power-on Reset 5V to 3.3V Translators

  16. SWIA Digital Schematics (Sweep DACs) 16-bit DAC provides sufficient accuracy over full dynamic range PDR Slide Deflector supply controls are multipliers based on Sweep voltage to increase dynamic range On-going discussion about correct multiplier to avoid saturation

  17. Digital Board Verification Digital Board Test per MAVEN-SWI-PROC-001a verifies: TLM/CMD connectivity with MISG Power distribution to test points Power consumption by service Power generation (+/-4V reference voltage for DACs) Polarity on all polarized capacitors Analog (raw and converted) and digital housekeeping Test pulser generation and frequency High voltage allow, arm, enable Fixed DAC control (MCP and Threshold) Sweep DAC control (Sweep Raw, Deflector 1 and 2) in diagnostic mode Sweep DAC control by LUT Anode Count Products (message receipt) Soft Reset

  18. FPGA Design and Test SWIA FPGA is RTSX72SU-CQ208E Heritage: STEREO SWEA (SIF FPGA) implemented in RTSX32S System Clock = 1MHz – (CMDCLK received from DCB) Estimated Power 75mW (28mA on 2.5V; 1.5mA on 3.3V) typical 80mW (30mA on 2.5V; 1.8mA on 3.3V) at 70C Utilization Estimate 75% (SWIA is worstcase) modules; ~100 I/Os TEST VERIFICATION: REV 0 initially tested on board REV 1 fixed polarity on housekeeping enable Pending REV 2 version: Fix LUT Write problem (missing one pointer bit for BUF1) Fix P2 Product Symmetry (telemetry readout) Fix P2 Product Bounding problem (EUPPER/LOWER, DUPPER/LOWER) Add memory test mode Add LUT checksum module

  19. FPGA Block Diagram (module verification) Pending Rev 2 • verified • verified • verified • verified • verified Pending Rev 2 • verified • verified • verified

  20. FPGA Data Product Verification • SWIA Product Generation Options (selectively enabled/disabled) • P0: Raw Counts • Outputs 24 16-bit counter values every 4 accumulation intervals (message generated every ~7ms) • P1: Counts Accumulated over Anodes, Deflector Step (Acc. Interval) and Energy • 10 NFOV Anodes summed into 2 bins => 16 Anode Counts • 16 Anode Counts are integrated over two Energy Steps • Outputs one 64 word message every other Energy Step (~83ms) • P2: Peak Energy Capture • Operates like a logic analyzer – storing a buffer and telemetering a programmable window around the peak • All Data Products Verified Pseudo Data Products 3-d Sky Plot Energy Spectra

  21. Pre-amp Board Design (Requirements) Amplify and transfer detector signals to digital board for accumulation Capable of counting at 2 MHz to prevent saturation in the solar wind (SWIA-608) Drove selection of A121s Provide programmable threshold of 1e5-2e6 electrons (SWIA-609) Two thresholds for two size anodes Test pulser inputs to allow for ground testing without High Voltage powered on (SWIA-606) Counter divides the test pulser into different rates for different anodes (SWIA-606) Sweep HV routed via a coax to the anode board, staying far from the preamp inputs (SWIA-610) MCP HV routed through the board, away from preamp inputs (SWIA-611) Preamp inputs will be located away from any high voltages or sources of noises (SWIA-612) anode MCP

  22. SWIA Preamp Schematics PDR Slide Caps for noise suppression Connector from Anode Connector to Digital Test Pulse Divider

  23. SWIA Preamp Schematic Details PDR Slide Threshold Adjust Dead Time Set to 100 ns 5V Digital Output Pulse Width Set to 50 ns Test Pulse Input Capacitively Coupled Preamp Input AC-Coupled Resistor values for dead time and pulse width still needs to be finalized for flight

  24. Preamp Board Verification Pre-amp crosstalk testing per MAVEN-SWI-PROC-005 verifies: Threshold voltage level by anode group Noise level with pulser off Cross talk between all anodes Pre-amp threshold testing per MAVEN-SWI-PROC-006 calculates: Optimum threshold setting for each anode Noise floor for each anode Pre-amp characterization (using test board) Per MAVEN-SWI-PROC-007 verifies: Dead time for different thresholds Pulse width for different thresholds Counts for different thresholds Determines optimal threshold

  25. Integrated DCB/Preamp Test Set-up Digital Board and Pre-amp boards integrated and tested

  26. PFDPU Integration and Test PFDPU integration per MAVEN-PF-TP-004 tested: • Safe-to-Mate • Command Test • Telemetry Test • Timing Test (not completed) • Aperture Test (not completed) • Power In-Rush Test Preamp DCB LVPS

  27. Voltage Temperature Margin (VTM) Test Voltage Temperature Margin Test perMAVEN-SWI-PROC-004: • Completed on the integrated SWIA Digital and Pre-amp ETU Boards in a thermal chamber (Tenny ID 9009, Silver RM 180) • Operating voltages (+5VA, -5VA, 5VD, +3.3VD, and +2.5VD) are varied by +/-10% • Voltage margin test at room temp, • maximum cold (-45C = Limit -15C), and • maximum hot (+65C = Limit +15C) • temperatures • Two issues noticed during this test: • Analog HSK not completely linear. Tracked this down to a solder bridge at the Actel Socket between HSKDAT8 and HSKDAT9.  Fixed and re-test shows Analog HSK very well behaved for nominal voltages +/-10%. • Noticed 7-second “in-rush” current (additional 10-15mA current on +5VA line).  Tracked this down to the time it takes the FPGA to set the thresholds to ½ scale on power up.  Thresholds are 0.0V for 7 seconds and then get set to ~1/2 scale (~2V) by the FPGA. At zero threshold the preamps will count any noise and draw up to a few mA extra apiece.  No change required.

  28. Electronic Parts • Electronic Part Status: • Flight BOMs provided to Parts Engineer • Active parts provided by GSFC • With very little exception, flight active parts being used on EM • Issue with lead time on HV capacitor on anode board resolved. Part removed from design with no impact. • Electronic Part Stress Analysis, using GSFC spreadsheet: • All capacitors meet 50% derating guidelines at maximum voltage • CDR capacitors are rated at 50V, which does not meet the requirement to use 100V rating for low voltage applications, requires additional part lot testing • All resistors meet derating guidelines, no changes required • All microcircuits meet deratingguidelines • Have not completed spreadsheets for diodes, connectors, transistors • Need to verify FETs (2N7389) are being used in safe operation region per request from GSFC Parts Control Board

  29. SWIA Power Budget PDR Table • Measured: ~ 55mW • ETU FPGA only 8mA on 2.5V (20mW). Flight FPGA power will be ~ 3x this. • Calculated power using RT54SX72 power calculator for expected utilization is 75mW • Overall digital board power may come down slightly • Measured: ~ 500mW, depends on counts • 96mA @ 5VA no counts • 125mA @ 5VA full counting

  30. Digital Board PDR Peer RFAs (Back-up) • PDR Schematics went through very detailed design review • Very little change from PDR Schematics to EM layout and build (all changes documented in detailed revision logs) • Very little change from EM unit to FM unit

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